TCAD simulation of a breakdown-enhanced double channel GaN metal–insulator–semiconductor field-effect transistor with a P-buried layer

Abstract

This paper proposes a new breakdown-enhanced gallium nitride (GaN) metal–insulator–semiconductor field-effect transistor (MISFET) with the architecture of a double channel and a P-buried layer, i.e. DCP-MISFET. The lower barrier and lower channel are connected to the drain, and the lower two-dimensional electron gas can improve the device electric field distribution between the gate and drain, achieving an enhanced breakdown voltage. At the same time, the P-buried layer below the gate field plate can reduce the peak electric field around the gate field plate. The proposed simulated device with LGD = 15 μm presents an excellent breakdown voltage of 2373 V. In addition, the ON-resistance of 15.07 s Ω mm and Baliga’s figure of merit of 3.736 GW cm−2 are achieved in the optimized DCP-MISFET. Compared with the breakdown voltage of 1547 V of the optimized field plate conventional GaN MISFET, the proposed device increases the breakdown voltage by 53.39% and the Baliga’s figure of merit is enhanced by 133.89%.