Oversampling Ratio Research Articles

On the System-Level Design of Noise-Shaping SAR Analog-to-Digital Converters

In this work, the system-level design of noise-shaping (NS) successive-approximation (SAR) analog-to-digital converters (ADCs) is investigated and analyzed. It is shown that despite the fact that the NS SAR architecture shares the same fundamental NS principle with the ΣΔ architecture, there are a few implementation differences that imply different considerations for optimum system-level design, particularly in the selection of the system oversampling ratio (OSR) and consequent resolution of the associated digital-to-analog converter (DAC) for a certain target overall resolution. In addition, the impacts of the OSR value on the power dissipation and figure-of-merit (FOM) are addressed in details.

An 88 dB SNDR 100 kHz BW Sturdy MASH Delta-Sigma Modulator Using Self-Cascoded Floating Inverter Amplifiers

Battery-powered Internet-of-Things applications require high-resolution, energy-efficient analog-to-digital converters (ADCs). There are still limited works on sub-MHz-bandwidth ADC designs. This paper presents a sturdy multi-stage shaping (SMASH) discrete-time (DT) delta-sigma modulator (DSM) structure using a self-cascoded floating-inverter-based dynamic amplifier (FIA). The proposed structure removes the explicit quantization error extraction of the first loop and all the feedback DACs in the cascaded loop, decreasing the design complexity of the circuit. This enables the proposed DT DSM to operate at a higher speed, which is suitable for achieving high-order noise at a low oversampling ratio (OSR). The proposed self-cascoded FIA is more power-efficient and can acquire more than 45 dB DC gain under a 1.2 V supply. The DT DSM implemented in a piece of 55 nm CMOS technology measures an 88.0 dB peak signal-to-noise-and-distortion ratio (SNDR) in a 100 kHz bandwidth (BW) and an 85.3 dB dynamic range (DR), consuming 249.1 μW from a 1.2 V supply at 10 MS/s. The obtained 174.0 dB SNDR-based Schreier figure-of-merit (FoMs) is competitive within state-of-art high-resolution (SNDR > 85 dB) and general-purpose (sub-MHz-bandwidth) ΔΣ ADCs.

A High-Resolution Discrete-Time Second-Order ΣΔ ADC with Improved Tolerance to KT/C Noise Using Low Oversampling Ratio.

This work presents a novel ΣΔ analog-to-digital converter (ADC) architecture for a high-resolution sensor interface. The concept is to reduce the effect of kT/C noise generated by the loop filter by placing the gain stage in front of the loop filter. The proposed architecture effectively reduces the kT/C noise power from the loop filter by as much as the squared gain of the added gain stage. The gain stage greatly relaxes the loop filter's sampling capacitor requirements. The target resolution is 20 bit. The sampling frequency is 512 kHz, and the oversampling ratio (OSR) is only 256 for a target resolution. Therefore, the proposed ΔΣ ADC structure allows for high-resolution ADC design in an environment with a limited OSR. The proposed ADC designed in 65 nm CMOS technology operates at supply voltages of 1.2 V and achieves a peak signal-to-noise ratio (SNR) and Schreier Figure of Merit (FoMs) of 117.7 dB and 180.4 dB, respectively.

Optimal oversampling ratio in two-step simulation

Abstract This paper analyses a novel two-step Monte Carlo simulation algorithm to estimate the weighted volume of a polytope of the form A ⁢ z ≤ T {Az\leq T} . The essential idea is to partition the columns of A into two categories – a lightweight category and a heavyweight category. Simulation is done in a two-step manner where, for every sample of the lightweight category variables we use multiple samples of the heavyweight category variables. Thus, the heavyweight category variables are oversampled with respect to the lightweight category variables and increasing samples of the heavyweight variables at the expense of the lightweight variables will lead to a more efficient Monte Carlo method. In this paper we present a fast heuristic approximate for estimating the optimal oversampling ratio and substantiate with experimental results which confirm the effectiveness of the method.

A 2nd-order noise-shaping SAR-assisted pipeline ADC with order-boosted gain-error-shaping

This paper presents a 4th-order interstage gain error shaping (GES) technique in pipeline successive approximation register (SAR) analog-to-digital converters (ADCs), which can substantially suppress the in-band quantization leakage error induced by the gain error. It is realized by simply arranging a low-order cascaded-integrator feed-forward (CIFF) structure in the first stage. In addition, the comparator noise and quantization error can be shaped together with the gain error in the proposed architecture. Verified by simulation in a 28-nm CMOS process, the prototype achieves a signal-to-noise-and-distortion ratio (SNDR) of 77.8 dB over 25-MHz bandwidth (BW) with oversampling ratio (OSR) of 8. Within a gain error range of −33 % to +33 %, the SNDR of the ADC deviates less than 3 dB. Under a 1 V supply voltage, the ADC consumes 3.75 mW and exhibits a Scherier figure of merit (FoMs) of 176 dB.

A First-Order Noise-Shaping SAR ADC with PVT-Insensitive Closed-Loop Dynamic Amplifier and Two CDACs

This paper presents a first-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with a process, (supply) voltage, and temperature (PVT)-insensitive closed-loop integrator and data-weighted averaging (DWA). The use of a cascode floating inverter amplifier (FIA)-type dynamic amplifier with high gain enables an aggressive noise transfer function while minimizing the power consumption associated with the use of an active filter. In the proposed ADC, the residue is generated by a capacitive digital-to-analog converter (CDAC) employing DWA, which is made possible by employing a second CDAC, which operates after the SAR operation is completed. The proposed ADC is designed with a 28 nm CMOS process with 1 V power supply. The simulation results show that the ADC achieves the SNDR of 71.2 dB and power consumption of 228 μW when operated with a sampling rate of 80 MS/s and oversampling ratio (OSR) of 10. The Schreier figure-of-merit (FoM) is 173.6 dB, and Walden FoM is 9.6 fJ/conversion-step.

A novel approach toward optimized image processing using sigma delta modulation

Image processing has widespread uses practically in every branch of science and arts. Processing images is more difficult than processing sound or data as there are more bits in the high pixel quality image. It requires more space to store the image, more bandwidth to transmit it, and more time and resources to process. An image's complexity may decrease if its bit size is decreased. Sigma-delta modulation, or SDM for short, is an alternative method of minimizing data-word length to compression. Digital signal processing (DSP) systems can be made simpler by using the SDM approach, which was first created for analog to digital conversion (ADC). This paper suggests a novel way to use SDM in MATLAB for improved image processing. Consequently, the suggested single-bit SDM-based image arithmetic architecture is tested and compared with the traditional image arithmetic techniques. Additionally, to see the noisy channel influence on the traditional and proposed systems, some statistical metrics are also studied at different noise variance values, such as signal to noise ratio (SNR), mean square error (MSE), and Peak SNR value. The suggested architecture for the SDM-based image arithmetic precisely matches the addition and subtraction results of the conventional design, even yielding a higher SNR and the same Peak SNR as the traditional methods. In contrast, the outcomes of division and multiplication fall within an acceptable range. For better results the over-sampling ratio (OSR), an inherent characteristic of SDM must be increased at the cost of more processing cycles. Therefore, the trade-off between fewer resources, limited transmission bandwidth, and comparatively more cycles is provided by the SDM-based technique.

A 96 dB DR Second-Order CIFF Delta-Sigma Modulator with Rail-to-Rail Input Voltage Range

A second-order delta-sigma modulator (DSM) is proposed for readout integrated circuits of sensor applications requiring a small area and low-power consumption. The proposed second-order CIFF DSM with the architecture of cascaded-of-integrator feedforward (CIFF) basically consists of two integrators, a 3-bit quantizer, data-weighted averaging (DWA) circuit, and clock generator. The use of the 3-bit quantizer instead of the single-bit quantizer reduces the size of the feedback capacitor in the first integrator. The 3-bit quantizer is designed based on a successive approximation register analog-to-digital converter for small area and low power implementation. Furthermore, the proposed second-order CIFF DSM has a single supply without an additional reference driver while having a wide analog input voltage range with rail to rail. The proposed second-order CIFF DSM, implemented using a 130 nm 1-poly 6-metal CMOS process with a supply of 1.5 V, has an area of 0.096 mm2. It has a sampling frequency of 500 kHz for the implementation of an input bandwidth of 2 kHz and an oversampling ratio of 125. The measured peak signal-to-noise and distortion ratio is approximately 90 dB when the differential analog input signal has a frequency of 353 Hz and an amplitude of 1.2 Vpp. The measured dynamic range is approximately 96.3 dB.

A 107.6 dB-DR Three-Step Incremental ADC for Motion-Tolerate Biopotential Signals Recording.

This article describes a power-efficient, high dynamic range (DR) incremental ADC (IADC) for wearable biopotential signals recording, where DC and low-frequency disturbances such as electrode offset, 50/60 Hz interference and motion artifact must be tolerated. To achieve a wide DR, the IADC performs a three-step conversion by combining zoom-SAR and extended counting (EC) on top of a second-order incremental delta-sigma modulator (ΔΣM). The hybrid architecture notably reduces the oversampling ratio (OSR) with respect to conventional incremental ΔΣMs, while using the EC further improves the Signal-to-Noise-and-Distortion Ratio (SNDR) by 7.4 to 25.6 dB. Fabricated in a 0.18-μm CMOS technology, the IADC achieves 107.6-dB DR, 104.9-dB peak SNR, and 99.3-dB peak SNDR at 2 kS/s while dissipating 130 μW from 1.8-V (analog) / 1.2-V (digital) supply. This translates to a highly competitive FoMDR of 176.5 dB. The high-DR IADC reduces the gain of the preceding instrumentation amplifier (IA) such that significant DC and low-frequency disturbances can be tolerated. The advantages of high DR have been demonstrated by wearable Electrocardiography (ECG) and Electroencephalography (EEG) recordings under motion artifact.

A low-power sigma-delta modulator based on high-order op-amp sharing technique for speech communication

In this paper, a novel idea of sigma-delta modulator (SDM) is proposed based on our high-order (greater than or equal to 4th order) op-amp sharing technology. The operation timing, adder, integrator structure and the switched-capacitor op-amps common-mode negative-feedback of the conventional single-loop cascade-of-integrators with feedforward (CIFF) modulator are improved, so that the nth-order integration function can be accomplished by using one op-amp. Finally, a high-precision and low-power sigma-delta modulator for speech communication is realized. The proposed 4th-order CIFF sigma-delta modulator based on our high-order op-amp sharing is utilized in 0.18 µm standard CMOS process and occupies an area of 0.218 mm2. Simulation results show that the SNDR is 103.91 dB and the ENOB is 16.97 bits with a sampling rate of 2.56 MHz, an oversampling ratio of 256, and signal bandwidth of 5 kHz. Proposed modulator has a supply voltage of 5 V and costs a power consumption of 2.29mW. The power consumption of proposed op-amp sharing idea is 29.67 % less than that of the conventional case.

Inverter-based noise-shaping SAR ADC for low-power applications

Noise-Shaping (NS) Successive-Approximation (SAR) Analog-to-Digital Converters (ADCs) are one of the most heavily researched ADC topologies in recent years. This high attention is attributed to the advantages of the NS SAR architecture that combines the merits of ΣΔ and SAR converters. However, the implementation of the NS SAR loop-filter in a passive or an active form imposes challenging tradeoffs among power dissipation, adequacy for scaling with technology, performance, and robustness against process-voltage-temperature (PVT) variations. In this work, a NS SAR ADC realization, based on inverter-based amplification, is proposed that alleviates these design challenges. The proposed implementation is used to design two ADCs in 28 nm CMOS technology to demonstrate its effectiveness. The first ADC employs an active loop-filter and achieves a signal-to-noise-plus-distortion (SNDR) of 62.9 dB, at a sampling frequency of 90 MHz, and an oversampling ratio (OSR) of 4, while consuming 0.59 mW from a 0.9 V supply. The second ADC has a passive loop-filter and provides 61 dB of SNDR for the same OSR and sampling frequency, with 0.58 mW power dissipation.

A 5 kHz-BW 18-bit zoom ADC with gain-enhanced CLS-assisted FIA

This paper presents a 5 kHz-BW 18-bit fully dynamic zoom ADC for low-power and high-resolution applications. A gain-enhanced cascode floating inverter amplifier (FIA) with correlated level shifting (CLS) assisted is proposed to achieve 68.5 dB effective gain with high energy efficiency. The data-weighted averaging (DWA) technique is implemented to suppress the nonlinearity caused by feedback DAC mismatch. Meanwhile, the coefficients of ΔΣ modulator are optimized for low power consumption. The proposed zoom ADC is designed in a 0.18 μm CMOS process. The post-layout simulation results show a peak SNDR of 110.4 dB and a peak SFDR of 114.8 dB with a 5 kHz-BW at an oversampling ratio (OSR) of 256. The power consumption of the proposed ADC is 342 μW at 2.56 MHz sampling frequency with 1.8 V supply, and the Schreier figure-of-merit (FoMSNDR) is 182.05 dB.

A 10-kHz BW 104.3-dB DR discrete-time delta-sigma modulator with ring-amplifier-based integrator

This paper presents a 3rd-order discrete-time delta-sigma modulator (DT DSM) with ring-amplifier-based integrators. To fulfill the performance requirement of the switched-capacitor (SC) integrator for the DSM with low power consumption, a dynamic ring amplifier is employed to replace the conventional continuous-time operation transconductance amplifier (OTA) in the integrator. The offset and 1/f noise of the 1st-stage integrator are further suppressed with an auto-zero structure. The quantizer is realized by a 3-bit flash analog-to-digital converter (ADC) to reduce the quantization noise power, while the mismatch in the feedback digital-to-analog converter (DAC) is suppressed by a dynamic weighting averaging (DWA) circuit. The DT DSM prototype is fabricated with a 0.18-μm CMOS process with an active area of 1.39 mm2, achieving 99.3 dB SNDR and 104.3 dB DR with a signal bandwidth of 10 kHz and an oversampling ratio of 128. The power consumption is 963.9 μW under a 3.3V power supply, corresponding to a Schreier figure-of-merit(FoMs) value of 174.5 dB.

A 102.1-dB SNDR oversampling merge-mismatch-error-shaping SAR ADC in 180 nm CMOS

In this paper, we propose a merge-mismatch-error-shaping (M-MES) noise shaping SAR ADC as a solution to address the limitation of SNDR caused by the non-linearity resulting from DAC mismatch. The proposed M-MES technique is based on MES with the introduction of capacitive merging to mitigate the degradation of dynamic range (DR) in ADCs. In addition, to meet the high signal-to-noise ratio (SNR) and low power requirements of the ADC, cascaded integrator feed-forward (CIFF) noise shaping ADC in this paper is a first-order filter based on a closed-loop amplifier. The proposed ADC was simulated and designed in a 180-nm CMOS process, which consumes 449 μW of power when operating at 1 MS/s sampling frequency. According to the post-simulation results, under a 3.3-V supply and at an oversampling ratio (OSR) of 500, the proposed ADC achieves Schreier FoMS of 168.5 dB with 102.1 dB signal to noise and distortion ratio (SNDR) and 102.2 dB spurious free dynamic range (SFDR).

A Closed-Loop VCO-based 1-1 SMASH CT ΔΣ ADC Architecture

A novel closed-loop voltage-controlled oscillator (VCO)-based 1-1 sturdy multistage noise-shaping (SMASH) continuous-time ΔΣ ADC is presented in this paper. The proposed architecture uses VCOs as integrators and puts them in a closed loop to suppress the VCO nonlinearity. The multi-bit quantization is employed in the proposed architecture so that the requirement of a high over-sampling ratio (OSR) is relaxed while maintaining a high resolution. The architecture has been verified in MATLAB Simulink.

A Data Weight Averaging-Inspired Digital Calibration Method for a 10-Bit Noise-Shaping Successive Approximation Register

This paper presents a digital calibration method for a 10-bit noise-shaping Successive Approximation Register Analog to Digital Converter (SAR ADC). The proposed calibration method is inspired by its Data Weight Averaging (DWA) counterpart, but stays static, while achieving a similar Integral Nonlinearity (INL) and 1.3 dB better Signal-to-Noise Ratio (SNR) in measurements without oversampling. This advantage in SNR holds until an Oversampling Ratio (OSR) of 2 for the proposed method, which also saves 50 % power. At a 1.2 V power supply, the ADC consumes a power of 70 µW at a conversion rate of 50 kHz. Fabricated using 55 nm Complementary Metal Oxide Semiconductor (CMOS) Metal-Oxide-Metal Capacitor (MOMCAP) technology, it occupies an active area of 370 µm × 350 µm, when achieving an INL of 0.3 Least Significant Bit (LSB) and an SNR of 66.9 dB at an OSR of 8.

Delay Error Shaping in ΔΣ Modulators Using Time-Interleaved High Resolution Quantizers

As wideband Delta-Sigma-Modulators (DSMs) are restricted in oversampling ratio (OSR), and low OSR reduces the benefit of higher order loop filters, the increase of the internal resolution is an obvious way to achieve high signal-to-quantization-noise ratio (SQNR). State-of-the-art implementations restrict the internal resolution to mostly 4-6 bits, as efficient QTZs with higher resolution add excessive delay into the DSM. Multi-step or time-interleaved-quantizer (TI-QTZs) are an effective way to enhance resolution at high sampling rate, but the resulting latency in excess of one clock cycle usually prohibits their usage in DSMs. This paper proposes a new architecture to employ high resolution multi-step QTZs, such as TI SAR or pipeline ADCs. In the proposed architecture, an excess loop delay (ELD) of several clock cycles in the LSBs is purposefully allowed. While the MSBs are conventionally ELD-compensated, the LSBs are not. The resulting error is corrected in the digital domain. It is shown that matching requirements are relaxed by first-order shaping. The idea is also applicable to a Leslie-Singh and noise-coupling architecture, which are compared to the proposed architecture in an extensive system-level analysis and simulation. Depending on the target application, an advantageous design recommendation can be given based on the presented results depending on OSR, internal bitwidth and expected analog-digital matching.

A 143 dB Delta-Sigma Modulator for Biomedical Applications

This paper presents a single loop forth-order delta-sigma modulator topology of cascade of integrator with multiple feedback This paper presents a single loop forth-order delta-sigma modulator topology of cascade of integrator with multiple feedback (CIFB) . The number of levels in the quantizer increases for higher performance. The modulator noice transfer function (NTF) and signal transfer function (STF) exploited for higher performance. The out-of-band gain (OBG) of 1.5 selected considering the stability of higher order modulator. The high oversampling ratio (OSR) considered for small bandwidth applications. The maximum quantization noise is suppressed by NTF zeros optimization. A full-scale signal of the modulator is 0.55-V considering the higher order loop filter stability. Due to CIFB topology, there is no peaking in the STF while STF response is flat. The zeros of the NTF are optimized for maximum quantization noise and poles are placed inside the unit circle. The complete modulator loop filter has four integrators in the loop filter with multiple feedback digital-to-analog converter (DAC) for maximum stability. The complete modulator simulation shows it an achieve signal-to-noise (SNR) of 1.43 dB with oversampling ratio (OSR) of 128.

Generation of high-speed PAM-4 signal with 3-bit DAC enabled by CRD-NS in optical interconnect.

In this paper, we experimentally demonstrated a 2-km high-speed optical interconnection with pulse-shaped pre-equalized four-level pulse amplitude modulation (PAM-4) signal generated by a 3-bit digital-to-analog converter (DAC) with the aid of in-band quantization noise suppression techniques under different oversampling ratios (OSRs) to reduce the influence of quantization noise. The simulation results show that the quantization noise suppression capability of high computational complexity digital resolution enhancer (DRE) is sensitive to taps number of the estimated channel and match filter (MF) response when OSR is sufficient, which will lead to further significant computational complexity increase. To better accommodate this issue, channel response-dependent noise shaping (CRD-NS) which also takes channel response into consideration when optimizing quantization noise distribution is proposed to suppress the in-band quantization noise instead of DRE. Experimental results show that about 2 dB receiver sensitivity improvement can be achieved at the hard-decision forward error correction (HD-FEC) threshold for 110 Gb/s pre-equalized PAM-4 signal generated by 3-bit DAC when the traditional NS technique is replaced by the CRD-NS technique. Compared to the high computational complexity DRE technique, in which channel response is also considered, negligible receiver sensitivity penalty is observed for 110 Gb/s PAM-4 signal, when the CRD-NS technique is utilized. Considering both the system cost and bit error ratio (BER) performance, the generation of high-speed PAM signal with 3-bit DAC enabled by the CRD-NS technique is regarded as a promising scheme for optical interconnection.

A Time-Domain Reconfigurable Second-Order Noise Shaping ADC With Single Fan-Out Gated Delay Cells

This brief proposes a time-domain second-order noise shaping analog-to-digital converter (ADC). It employs a voltage-to-time converter (VTC) in tandem with a second-order noise shaping time-to-digital converter (TDC), which realizes the goal of reducing the power consumption and accommodating different resolutions by configuring locations of poles of the transfer function. Note that the time-register constructed TDC, which performs the signal processing function in the time domain, is implemented with digital cells thoroughly. In this way, the proposed architecture can be more friendly to the increasingly scaled process. The reconfigurable architecture enables to obtain the target signal-to-noise-and-distortion ratio (SNDR) with decreased oversampling ratio (OSR), which improves energy efficiency relatively. In addition, compared with the conventional CMOS gated delay cell, the proposed single fan-out (SFO) gated delay cell is featured with lower power dissipation and shorter delaying time. The prototype is implemented in a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\bm\mu$</tex-math> </inline-formula> m CMOS technology to demonstrate the validity of this proposed time-domain ADC. It achieves 64.5-, 56.1-, and 51.2-dB SNDR in 0.025-, 0.05-, and 0.1-MHz bandwidth on conditions of the OSR being 200, 100, and 50, respectively.