A 10-kHz BW 104.3-dB DR discrete-time delta-sigma modulator with ring-amplifier-based integrator

Abstract

This paper presents a 3rd-order discrete-time delta-sigma modulator (DT DSM) with ring-amplifier-based integrators. To fulfill the performance requirement of the switched-capacitor (SC) integrator for the DSM with low power consumption, a dynamic ring amplifier is employed to replace the conventional continuous-time operation transconductance amplifier (OTA) in the integrator. The offset and 1/f noise of the 1st-stage integrator are further suppressed with an auto-zero structure. The quantizer is realized by a 3-bit flash analog-to-digital converter (ADC) to reduce the quantization noise power, while the mismatch in the feedback digital-to-analog converter (DAC) is suppressed by a dynamic weighting averaging (DWA) circuit. The DT DSM prototype is fabricated with a 0.18-μm CMOS process with an active area of 1.39 mm2, achieving 99.3 dB SNDR and 104.3 dB DR with a signal bandwidth of 10 kHz and an oversampling ratio of 128. The power consumption is 963.9 μW under a 3.3V power supply, corresponding to a Schreier figure-of-merit(FoMs) value of 174.5 dB.