A Compact 10-bit Nonbinary Weighted Switched Capacitor Integrator Based SAR ADC Architecture

Abstract

A compact switched capacitor integrator (SCI) based successive approximation register (SAR) analog to digital converter (ADC) for data acquisition system is presented. This technique requires an operational transconductor amplifier (OTA), a comparator and four equal sized capacitors of moderate value for fully differential approach and the architecture is resolution independent. The reference voltage is generated by charge sharing between a reference capacitor and the input capacitor of a switched capacitor (SC) integrator. The DAC voltage for comparison is generated by accumulating the charges on the SC integrating capacitor. ADC being fully differential nature has wide input range and it is parasitic insensitive to a large extent. As a stand alone data converter it has small capacitance spread and hence its input capacitance is easy to drive. A 10 bit 0.9MHz sampling rate SAR ADC is designed using 180 nm CMOS technology, operating at 1.8 V supply, has effective number of bits (ENOB) of 9.5 at Nyquist frequency. The ADC occupies small die area compared to SAR with a binary weighted capacitor array.