Abstract
This paper presents a 10-bit subrange analog-to-digital converter (ADC) consisting of a 3-bit coarse successive-approximation-register (SAR) ADC, a 7-bit fine SAR ADC, and two sets of the binary-weighted capacitor arrays digital-to-analog converter (DAC) using a new technique of triple reference voltage. The smaller MSB capacitor improves the operating speed of the coarse SAR ADC due to less charge redistribution time. The proposed 10-bit SAR ADC is implemented in the TSMC 0.18 μm CMOS technology with a power supply of 1.8V. The effective number of bits (ENOB) is 8.29 bit, the sampling rate achieves at 30 MS/s. Both theoretical analysis and behavioral simulations show that the differential non-linearity (DNL) of a SAR ADC with segmented DAC is better than that of a binary ADC. Consequently, compared with conventional SAR ADC without any calibration, the proposed efficient capacitor switching technology can shorten the conversion time of the previous cycle and lower the switching energy.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
