Abstract
This paper presents an energy efficient architecture for successive approximation register (SAR) analog to digital converter (ADC). SAR ADCs with a capacitor array structure have been widely used because of its simple architecture and relatively high speed. However, conventional SAR ADCs consume relatively high energy due to the large number of capacitors used in the capacitor array and their sizes scaled up along with the number of bits. The proposed architecture reduces the energy consumption as well as the capacitor size by employing a new array architecture that scales down the reference voltages instead of scaling up the capacitor sizes. The proposed 12-bit SAR ADC is implemented in Complementary Metal Oxide Semiconductor (CMOS) library using Cadence Virtuoso design tool. Simulation results and mathematical model demonstrate the overall energy savings of up to 97.3% compared with conventional SAR ADC, compared with the SAR ADC with split capacitor, and compared with the resistor and capacitor (R&C) Hybrid SAR ADC. The ADC achieves an effective number of bits (ENOB) of bits and consumes at sampling rate of , offering an energy consumption of per conversion step. The proposed SAR ADC offers 95.5% reduction in chip core area compared to conventional architecture, while occupying an active area of .
Highlights
Wireless sensor networks and implantable biomedical devices has been gaining popularity in the recent years
We propose a successive approximation register (SAR) analog to digital converter (ADC) architecture based on successive scaling of the reference voltages instead of conventional scaling of capacitor size to reduce the switching energy consumption and chip area
This paper proposed an energy-efficient architecture of successive approximation register (SAR) analog to digital converter (ADC) based on successive scaling of reference voltage
Summary
Wireless sensor networks and implantable biomedical devices has been gaining popularity in the recent years These applications require low power consumption because of their limited power budget while achieving optimum performance. SAR ADCs can, result in an improved performance and reduced power consumption. In [7] a digital to analog converter (DAC) configurable window switching technique to ensure reusing the capacitors in DAC is incorporated in SAR ADCs for overall smaller capacitances. We propose a SAR ADC architecture based on successive scaling of the reference voltages instead of conventional scaling of capacitor size to reduce the switching energy consumption and chip area. The rest of this paper is organized as follows: Section 2 describes the general architecture of SAR ADCs. Section 3 presents the proposed architecture and the analysis of its switching energy.
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