High-Resolution SAR ADC With Enhanced Linearity

Abstract

This brief proposes two digital-to-analog converter switching techniques for binary-weighted capacitor array successive approximation register (SAR) analog-to-digital converter (ADC), rotating&averaging without redundancy technique and rotating&averaging with redundancy technique. The rotating&averaging without redundancy technique can improve the signal-to-noise ratio (SNR) and spurious free dynamic range (SFDR) of conventional SAR ADCs by averaging four samples for one input voltage, while the rotating&averaging with redundancy has better static linearity improvement but less SNR improvement than the rotating&averaging without redundancy technique. The application of these two methods to 14-bit SAR ADC is demonstrated by Monte-Carlo runs, results show that with a mismatch error typical of modern technology, the proposed rotating&averaging with redundancy scheme can improve the root-mean-square of integral nonlinearity from 2.08 to 0.57 LSB, and the SFDR is more than 15 dB better. On the other hand, the averaged SNR of 7.7 dB is improved by using the proposed rotating&averaging without redundancy technique for a 14-bit SAR ADC. Furthermore, the schemes proposed require only small additional circuit on a typical SAR ADC configuration, which are more feasible to implement high-resolution SAR ADC compared with the traditional calibration schemes.