Oversampling Ratio Research Articles

A New Multistage Noise-Shaping Architecture

This paper presents a new architecture for high dynamic range, low oversampling ratio (OSR) noise-shaped digital-to-analog converters (DACs). The instantaneous noise feedforward architecture is a multistage structure in which the instantaneous noise and gain/phase distortion in the first stage are cancelled by passing them through another converter and then subtracting them at the output after analog attenuation. The signal-to-noise-and-distortion ratio (SNDR) of a device using this architecture scales as the product of the first noise shaper's SNDR and the ratiometric precision of the attenuator technology. This new architecture was implemented by driving the bits of an existing DAC (with binary weighting) using specially generated digital signals. One set of experimental measurements demonstrates a spurious-free dynamic range (SFDR) performance of 83 dBc in a 125-MHz bandwidth centered at 325 MHz while using an OSR of only 4. A second set of experimental measurements produces an SFDR performance of 70 dBc in a 125-MHz bandwidth centered slightly above 1.3 GHz with an OSR of 16

A Reduced-Sample-Rate Sigma-Delta-Pipeline ADC Architecture for High-Speed High-Resolution Applications

A reduced-sample-rate (RSR) sigma-delta-pipeline (SDP) analog-to-digital converter architecture suitable for high-resolution and high-speed applications with low oversampling ratios (OSR) is presented. The proposed architecture employs a class of high-order noise transfer function (NTF) with a novel pole-zero locations. A design methodology is developed to reach the optimum NTF. The optimum NTF determines the location of the non-zero poles improving the stability of the loop and implementing the reduced-sample-rate structure, simultaneously. Unity gain signal transfer function to mitigate the analog circuit imperfections, simplified analog implementation with reduced number of operational transconductance amplifiers (OTAs), and novel, aggressive yet stable NTF with high out of band gain to achieve larger peak signal-to-noise ratio (SNR) are the main features of the proposed NTF and ADC architecture. To verify the usefulness of the proposed architecture, NTF, and design methodology, two different cases are investigated. Simulation results show that with a 4th-order modulator, designed making use of the proposed approach, the maximum SNDR of 115dB and 124.1 dB can be achieved with only OSR of 8, and 16 respectively.

An Analog/Digital Baseband Processor Design of a UWB Channelized Receiver for Transmitted Reference Signals

The frequency channelized receiver enables the use of practical analog-to-digital converters (ADC) to digitize ultra-wideband (UWB) signals. The design issues of the analog and digital baseband processor for the channelized receiver in a UWB transmitted reference (TR) system are investigated. In the analog part, the receiver performance is shown to be weakly dependent on the analog filter bandwidth, the filter order, and the ADC oversampling ratio assuming white input noise. In the digital part, the coarse acquisition performance is shown to be significantly better in a channelized receiver than in a fullband receiver. The implementation issues for fine synchronization and correlation window length are also studied.

Perfect Reconstruction Conditions and Design of Oversampled DFT-Modulated Transmultiplexers

This paper presents a theoretical analysis of oversampled complex modulated transmultiplexers. The perfect reconstruction (PR) conditions are established in the polyphase domain for a pair of biorthogonal prototype filters. A decomposition theorem is proposed that allows it to split the initial system of PR equations, that can be huge, into small independent subsystems of equations. In the orthogonal case, it is shown that these subsystems can be solved thanks to an appropriate angular parametrization. This parametrization is efficiently exploited afterwards, using the compact representation we recently introduced for critically decimated modulated filter banks. Two design criteria, the out-of-band energy minimization and the time-frequency localization maximization, are examined. It is shown, with various design examples, that this approach allows the design of oversampled modulated transmultiplexers, or filter banks with a thousand carriers, or subbands, for rational oversampling ratios corresponding to low redundancies. Some simulation results, obtained for a transmission over a flat fading channel, also show that, compared to the conventional OFDM, these designs may reduce the mean square error.

Rapid gridding reconstruction with a minimal oversampling ratio

Reconstruction of magnetic resonance images from data not falling on a Cartesian grid is a Fourier inversion problem typically solved using convolution interpolation, also known as gridding. Gridding is simple and robust and has parameters, the grid oversampling ratio and the kernel width, that can be used to trade accuracy for computational memory and time reductions. We have found that significant reductions in computation memory and time can be obtained while maintaining high accuracy by using a minimal oversampling ratio, from 1.125 to 1.375, instead of the typically employed grid oversampling ratio of two. When using a minimal oversampling ratio, appropriate design of the convolution kernel is important for maintaining high accuracy. We derive a simple equation for choosing the optimal Kaiser-Bessel convolution kernel for a given oversampling ratio and kernel width. As well, we evaluate the effect of presampling the kernel, a common technique used to reduce the computation time, and find that using linear interpolation between samples adds negligible error with far less samples than is necessary with nearest-neighbor interpolation. We also develop a new method for choosing the optimal presampled kernel. Using a minimal oversampling ratio and presampled kernel, we are able to perform a three-dimensional (3-D) reconstruction in one-eighth the time and requiring one-third the computer memory versus using an oversampling ratio of two and a Kaiser-Bessel convolution kernel, while maintaining the same level of accuracy.

A 8X Oversampling Ratio, 14bit, 5-MSamples/s Cascade 3-1 Sigma-delta Modulator

Abstract. A 14-b, 5-MHz output-rate cascaded 3-1 sigma-delta analog-to-digital converters (ADC) has been developed for broadband communication applications, and a novel 4th-order noise-shaping is obtained by using the proposed architecture. At a low oversampling ratio (OSR) of 8, the ADC achieves 91.5dB signal-to-quantization ratio (SQNR), in contrast to 71.8dB of traditional 2-1-1 cascaded sigma-delta ADC in 2.5-MHz bandwidth and over 80dB signal-to-noise and distortion (SINAD) even under assumptions of awful circuit non-idealities and opamp non-linearity. The proposed architecture can potentially operates at much more high frequencies with scaled IC technology, to expand the analog-to-digital conversion rate for high-resolution applications.

A third-order /spl Sigma//spl Delta/ modulator in 0.18-/spl mu/m CMOS with calibrated mixed-mode integrators

This paper describes a third-order sigma-delta (/spl Sigma//spl Delta/) modulator that is designed and implemented in 0.18-/spl mu/m CMOS process. In order to increase the dynamic range, this modulator takes advantage of mixed-mode integrators that consist of analog and digital integrators. A calibration technique is applied to the digital integrator to mitigate mismatch between analog and digital paths. It is shown that the presented modulator architecture can achieve a 12-dB better dynamic range than conventional structures with the same oversampling ratio (OSR). The experimental prototype chip achieves a 76-dB dynamic range for a 200-kHz signal bandwidth and a 55-dB dynamic range for a 5-MHz signal bandwidth. It dissipates 4 mW from 1.8-V supply voltages and occupies 0.7-mm/sup 2/ silicon area.

Symbol-timing estimation in space-time coding systems based on orthogonal training sequences

Space-time coding has received considerable interest recently as a simple transmit diversity technique for improving the capacity and data rate of a channel without bandwidth expansion. Most research in space-time coding, however, assumes that the symbol timing at the receiver is perfectly known. In practice, this has to be estimated with high accuracy. In this paper, a new symbol-timing estimator for space-time coding systems is proposed. It improves the conventional algorithm of Naguib et al. such that accurate timing estimates can be obtained even if the oversampling ratio is small. Analytical mean-square error (MSE) expressions are derived for the proposed estimator. Simulation and analytical results show that for a modest oversampling ratio (such as Q equal to four), the MSE of the proposed estimator is significantly smaller than that of the conventional algorithm. The effects of the number of transmit and receive antennas, the oversampling ratio, and the length of training sequence on the MSE are also examined.

QUANTIZED FEEDBACK CONTROL FOR SAMPLED-DATA SYSTEMS

This paper studies the problem of quantized feedback control for sampled-data systems which employ a quantizer to transmit feedback signals at a given sampling rate. The so-called static (memoryless) quantizers are considered. Given a continuous-time system, the design objective is to stabilize the system or to achieve certain performance using the coarsest quantization density. We study the possible advantages of over-sampling where the input/output signals of the system are sampled at a faster rate than the quantizer. Our first result is for stabilization, and it shows that the coarsest quantization density achievable using quantized state feedback can be generically achieved using output feedback with any over-sampling ratio. Our second result provides a solution to the quantized feedback H∞ problem for both with and without over-sampling.

A Non-Feedback -Σ Modulator for Digital-to-Analog Conversion Using Digital Frequency Modulation

This paper describes a novel noise-shaping Δ-Σ modulator for D/A-conversion which has no global feedback. The proposed topology is well suited for a pipelined clocking scheme allowing increased oversampling ratios for both first and higher order modulators. The maximum clock-frequency of the new modulator is limited only by the delay through one single accumulator regardless of modulator order, which represents a huge saving compared to the conventional modulator. The converter is very modular and scales easily to higher modulator orders. Still the proposed topology is mathematically equivalent to the classical Δ-Σ modulator. Theoretical analysis and circuit simulations for a first- and second-order modulator are presented. The first-order circuit has been implemented in a FPGA-circuit from Altera and measured results are presented.

Timing Recovery for the Magnetic Recording Channel Using the Wave Difference Method

Timing recovery using the wave difference method is proposed for use in a magnetic recording read channel. The scheme uses an oversampling ratio of two and is suitable for mixed-signal or digital implementations. A simple class of prefilter that significantly improves the signal-to-interference ratio of the generated timing-error estimate is described. This prefilter also allows a simple implementation based on an absolute value, rather than squaring or fourth-order nonlinearity. Simulation results for this scheme are presented for a range of recording densities and channel noise levels.

A wireless RF CMOS mixed-signal interface for soil moisture measurements

This paper describes a wireless RF CMOS interface for soil moisture measurements. The interface basically comprises a Delta-Sigma (ΔΣ) modulator for acquiring an external sensor signal, and a RF section where data is transmitted to a local processing unit. The ΔΣ modulator is a single-bit, second-order modulator and it is implemented using switched-capacitors techniques in a fully-differential topology. With a sampling frequency of 423.75 kHz and an oversampling ratio (OSR) of 256, the modulator achieves a dynamic range of 98.7 dB (16.1 bit). The output of the modulator is applied to a counter, as a first-order decimation filter, and the result is stored. Prior to transmission, data is encoded as a pulse width modulated signal and assembled in a frame containing preamble and checksum control fields. This frame is then transmitted through a power amplifier operating at 433.92 MHz in class-E mode. To evaluate the ΔΣ modulator performance, the bitstream was acquired and transferred to a personal computer to perform digital filtering and decimation using MATLAB. The soil moisture sensor is based on dual-probe heat-pulse (DPHP) method and is implemented by using an integrated temperature sensor and a heater. After applying a heat-pulse for a fixed period of time, the temperature rise, that is a function of soil moisture, generates a differential voltage that is amplified and applied to the mixed-signal interface input. The described interface can also be used with other kinds of environmental sensors in a wireless sensors network. The CMOS mixed-signal interface has been implemented in a single-chip using a standard CMOS 0.7 μm process (AMI C07M-A, n-well, 2 metals and 1 poly).

A Bandpass Mismatch Noise-Shaping Technique for<tex>$Sigma$</tex>–<tex>$Delta $</tex>Modulators

A simple bandpass mismatch noise-shaping technique for /spl Sigma/-/spl Delta/ modulators is presented. This technique uses the data-directed scrambler structure and achieves /spl sim/20 dB improvement in signal-to-noise ratio (SNR) for an oversampling ratio (OSR) of 32. Compared to the technique of bandpass mismatch noise shaping of Lin and Schreier, here, the SNR is improved by /spl sim/ 7dB resulting in a 1-bit improvement in resolution. The selection logic is half the size of the logic in Lin and Schreier and is fully compatible with the low-pass selection logic of Kwan et al.. This compatibility allows implementation of bandpass/low-pass modulator as a single product.

High-Order Multibit Modulators and Pseudo Data-Weighted-Averaging in Low-Oversampling>tex<$Delta Sigma$>/tex<ADCs for Broad-Band Applications

High-speed high-resolution /spl Delta//spl Sigma/ analog-to-digital converters (ADCs) for broad-band communication applications must be designed at a low oversampling ratio (OSR). However, lowering the OSR limits the efficiency of a /spl Delta//spl Sigma/ ADC in achieving a high-resolution A/D conversion. This paper presents several techniques that enable the OSR reduction in /spl Delta//spl Sigma/ ADCs without compromising the resolution. 1) Noise transfer function (NTF). In this paper, a single-stage multibit /spl Delta//spl Sigma/ modulator with a high-order finite-impulse-response NTF is proposed to achieve high signal-to-quantization-noise ratios at low OSRs. Its key features include: decreased circuit complexity, improved robustness to modulator coefficient variations, and reduced sensitivity to integrator nonlinearities. Its performance is validated through behavioral simulations and compared to traditional /spl Delta//spl Sigma/ modulator structures. 2) Signal transfer function (STF). This paper describes how the STF of a /spl Delta//spl Sigma/ modulator can be designed, independently of the NTF, in order to significantly reduce the harmonic distortion due to opamp nonidealities and to help lower the power dissipation. 3) Dynamic element matching (DEM) is also presented. Data weighted averaging (DWA) has prevailed as the most practical DEM technique to linearize the internal digital-to-analog converter (DAC) of a multibit /spl Delta//spl Sigma/ modulator, especially when the number of DAC elements is large. However, the occurrence of in-band signal-dependent tones, when using DWA at a low OSR, degrades the spurious-free dynamic range. This paper proposes a simple technique, called pseudo DWA, to solve the DWA tone problem without sacrificing the signal-to-noise ratio. Its implementation adds no extra delay in the /spl Delta//spl Sigma/ feedback loop and requires only minimal additional digital hardware. Existing schemes for DWA tone reduction are also compared.

An Efficient>tex<$Delta Sigma $>/tex<ADC Architecture for Low Oversampling Ratios

As the demand for /spl Delta//spl Sigma/ (delta-sigma) analog-to-digital converters (ADCs) with higher bandwidth and higher signal-to-noise ratio (SNR) increases, designers have to look for efficient structures with low oversampling ratio (OSR). The Leslie-Singh or M-0 MASH architecture is often used in such applications. Based on this architecture, a reduced-sample-rate structure was introduced, which needs less chip area and power, but increases the noise floor. This paper describes a modification of the reduced-sample-rate structure which realizes an optimized transfer function, and avoids an SNR loss. In fact, it increases the SNR for high-order modulators. The method can also be applied to one-stage modulators. Simulation results for different MASH ADCs and sensitivity analysis verify the usefulness of the proposed technique.

Analysis and modelling of gravity- and piston coring based on soil mechanics

The effects of gravity- and piston corers on the dimensional accuracy of marine sediment cores is analysed using principles of soil mechanics. A model for the coring process is built around the feedback that arises and develops between the core barrel and the sampled sediment. This model for sediment response is applied to different hypothetical coring scenarios, which are then compared to real examples, providing insights into the specific effects of each sampling method and the development of these effects down-core. Four cores from a single location on the Iberian Margin are found to contain stratigraphically intact successions that differ in length by a factor of up to 2.7, due solely to the different effects of each coring method. These dimensional discrepancies are attributed to the combined effects of ‘over-sampling’ in the upper portions of the piston cores (due to cable rebound causing upward piston acceleration), and ‘under-sampling’ dominant in the basal portions of the open-barrel gravity-type cores. It is suggested that heavier piston corers, deployed on longer, lighter cables, are prone to greater over-sampling ratios over longer stratigraphic intervals, due to the increased likelihood and extent of cable rebound. Cable rebound may also give rise to double penetration of gravity corers, resulting in repeated stratigraphic intervals. Knowledge of the dimensional accuracy of marine sediment cores is essential to an evaluation of past sedimentation rates, and hence interpretations of past depositional processes. It is therefore essential that we recognise the sampling effects of each coring method, and their variability down-core, lest coring artefacts be interpreted as sedimentary signals. Different core types may be more suited to different palaeoceanographic investigations. Hence, failing the development of a practical cable-deployed recoilless piston corer, a combination of a variety of core types will permit the best acquisition of the in situ stratigraphic truth. Our results suggest that a large-diameter ( D c∼20–30 cm) square-barrel gravity corer for the top 10–12 m combined with a cylindrical piston corer below ∼10 m may provide the least deformed material.

A 14-bit high-temperature ΣΔ modulator in standard cmos

Experimental verification is given for the use of /spl Sigma//spl Delta/ modulation for high-temperature applications (/spl ges/approximately 150/spl deg/C) in a standard CMOS process. Switched-capacitor circuits are used to implement a second-order single-stage and a third-order 2-1 MASH /spl Sigma//spl Delta/ modulator with single-bit quantization. The two modulators have an oversampling ratio of 256 with an input signal bandwidth of 500 Hz. The modulators were fabricated in a 1.5-/spl mu/m standard CMOS technology. A fully differential signal path and near minimum sized switches are used to mitigate the effect of large junction-to-substrate leakage current present at high temperatures. Experimental results show both modulators are capable of over 14 bits of resolution at 225/spl deg/C and over 13 bits of resolution at 255/spl deg/C. Results show that the single-stage modulator is more resistant to high-temperature circuit impairment than is the MASH cascaded structure.

A 1-v 3.5-mW CMOS switched-opamp quadrature if circuitry for bluetooth receivers

A 1-V switched-capacitor (SC) quadrature IF circuitry for Bluetooth receivers is demonstrated using switched-opamp technique. To achieve double power efficiency while maintaining low sensitivity to finite opamp gain effects for the SC IF circuitry, half-delay integrator-based filters and /spl Sigma//spl Delta/ modulator have been proposed. The proposed quadrature IF circuitry employs a seventh-order IF filter for channel selection and a third-order /spl Sigma//spl Delta/ modulator for analog-to-digital conversion. A noise-shaping extension technique is employed to enhance the resolution of the low-pass /spl Sigma//spl Delta/ modulator by 16 dB while operating at the same oversampling ratio and power consumption. At a 1-V supply, the quadrature IF circuitry achieves a measured IIP3 of -3 dBm at a nominal gain of 24 dB with a 48-dB variable gain control while consuming a total power dissipation of 3.5 mW.

A wideband cascaded sigma-delta modulator with improved nonlinearity effects

This work presents a wideband cascaded sigma-delta modulator (CLFSDM) that reduces the nonlinearity effects of components. This architecture offers a new noise-shaping function to achieve high resolution in wideband applications and reduce digital-analogue converter (DAC) mismatch from the multi-bit feedback. Moreover, the error cancellation schemes can be added in the digital circuit part to cancel the coarse quantization errors and thus effectively reduce the non-ideal effects such as DAC mismatch. The mismatches between the two stages, such as in the gain error and pole error, may seriously degrade performance. The blind on-line calibration technique is used to eliminate these imperfect analogue circuit errors in the digital circuit. Accordingly, this architecture can reduce the over sampling ratio (OSR), and the in-band noise can be significantly suppressed to achieve a high resolution in Matlab and Switcap2 simulations. Simulation results indicate this sigma-delta modulator is very efficient in wide bandwidth applications.

A fourth-order bandpass Δ-Σ modulator using second-order bandpass noise-shaping dynamic element matching

This paper describes a multibit bandpass /spl Delta//spl Sigma/ modulator (DSM) for a frequency-interleaved analog-to-digital (A/D) converter (ADC). A frequency-interleaved ADC using low oversampling ratio (OSR) DSMs is an attractive approach for broadband and high resolution A/D conversion. A multibit DSM is suitable for low-oversampling operation; however, the overall resolution of a multibit DSM is restricted by the accuracy of the internal D/A converter (DAC). Some methods have been reported for improving the internal DAC accuracy of a low-pass DSM, but no bandpass-shaping technique applicable to a bandpass DSM has been implemented, although some methods have been proposed by using simulation. This paper proposes a multibit bandpass DSM with bandpass noise-shaping dynamic element matching (BPNSDEM), which enables bandpass shaping to mismatch error of the internal DAC, and presents its implementation. The modulator was implemented in a 0.25-/spl mu/m CMOS technology. It operates at a 2.5-V power supply and achieves a signal-to-noise ratio of 77.4 dB over a 250-kHz bandwidth centered at 566 kHz.