Oversampling Ratio Research Articles

A single die 1.2 V 55 to 95 dB DR delta sigma ADC with configurable modulator and OSR

A single die 1.2 V multi-stage noise shaping (Mash) 2-2 delta sigma analog to digital converter (ADC) for wide applications is implemented. The configurable Mash 2-2 modulator with a new decimation filter design is presented to achieve wide and high dynamic range (DR) for multiple practical applications. The novel modulator can be configured as a Mash 2-2 modulator for high precision or a 2-order modulator for low DR. The decimation filter is designed to select the OSR flexibly among cascaded integrator comb (CIC) filter and two half-band filters (HBF). The serial peripheral interface (SPI) can be used to adjust the sampling frequency and the oversampling ratio (OSR). The design was fabricated in a 0.13 μm CMOS process with an area of 0.91 mm2 and a total power of 5.2 mW. The measurement results show that the dynamic range (DR) of the proposed ADC can change from 55 to 95 dB with the configurable OSR from 16 to 256. The spurious free dynamic range (SFDR) and signal-to-noise distortion ratio (SNDR) can get 99 dB and 86.5 dB, respectively.

Design of an Ultra-Low Power CT ΣΔ A/D Modulator in 65 nm CMOS for Cardiac Pacemakers: From System Synthesis to Circuit Implementation

Abstract A high performance, ultra-low power, fully differential 2nd-order continuous-time ΣΔ analogue-to-digital modulator for cardiac pacemakers is presented in this paper. The entire design procedure is described in detail from the high-level system synthesis in both discrete and continuous-time domain, to the low-level circuit implementation of key functional blocks of the modulator. The power consumption of the designed modulator is rated at 182 nA from a 1.2V power supply, meeting the ultra-low power requirement of the cardiac pacemaker applications. A 65 nm CMOS technology is employed to implement the ΣΔ modulator. The modulator achieves a simulated SNR of 53.8 dB over a 400Hz signal bandwidth, with 32KHz sampling frequency and an oversampling ratio of 40. The active area of the modulator is 0.45 × 0.50mm2

A High-Performance Sigma-Delta Modulator in 0.18μm CMOS Technology

Sigma-Delta (∑∆) modulators are commonly used in high-resolution analog-to-digital converters (ADCs). In this paper, a high-performance modulator targeted for ultra-high-frequency (UHF) radio-frequency identification (RFID) zero-intermediate frequency (ZIF) receivers is designed in standard 0.18μm CMOS technology. The modulator has been designed with switched-capacitor (SC) integrators employing gain-boosted operational amplifiers, voltage comparators and nonoverlapping clock generators to satisfy such requirements as high gain, low voltage and wide bandwidth. The behavioral-level modeling and circuit-level design are carried out with MATLAB/Simulink and Cadence/SpectreRF, respectively. Ultimately, the high-speed and low-power realization of a second-order single-bit modulator with an oversampling ratio (OSR) of 32 is presented. Simulation results shown that, from a 1.8V supply, operated at a sampling frequency of 64MHz, a dynamic range of 53.4dB over a signal bandwidth of 1MHz is achieved.

A High-Performance Sigma-Delta Modulator in 0.18μm CMOS Technology

Sigma-Delta (∑∆) modulators are commonly used in high-resolution analog-to-digital converters (ADCs). In this paper, a high-performance modulator targeted for ultra-high-frequency (UHF) radio-frequency identification (RFID) zero-intermediate frequency (ZIF) receivers is designed in standard 0.18μm CMOS technology. The modulator has been designed with switched-capacitor (SC) integrators employing gain-boosted operational amplifiers, voltage comparators and nonoverlapping clock generators to satisfy such requirements as high gain, low voltage and wide bandwidth. The behavioral-level modeling and circuit-level design are carried out with MATLAB/Simulink and Cadence/SpectreRF, respectively. Ultimately, the high-speed and low-power realization of a second-order single-bit modulator with an oversampling ratio (OSR) of 32 is presented. Simulation results shown that, from a 1.8V supply, operated at a sampling frequency of 64MHz, a dynamic range of 53.4dB over a signal bandwidth of 1MHz is achieved.

Non-Linear Reconstruction of Delta-Sigma Modulated Signals: Randomized Surrogate Constraint Decoding Algorithm

Delta-sigma (ΔΣ) A/D conversion is a popular technique used to achieve high resolution data conversion for low to moderate bandwidth applications. It is commonly accepted that the digital circuitry of the ΔΣ A/D converters should perform a linear time-invariant (LTI) filtering on the output of the ΔΣ modulator in order to reconstruct the input signal. However, it has been shown that, when higher order ΔΣ A/D converters are operated at higher oversampling ratios (OSRs), non-linear reconstruction algorithms extract more information about the input signal than LTI methods. Still, use of non-linear algorithms has been limited due to their complexity and stability issues. Two practical non-linear methods presented in the literature are fast projection onto convex sets (POCS) and direct projection (DP). In this work, we show that the non-linear reconstruction process for ΔΣ modulated sequences can be treated as a linear feasibility problem (LFP). We then show that if the reconstruction process is defined as an LFP, its implementation is less complex than in the case of the DP method. We further describe how the LFP can be well-conditioned and demonstrate the reconstruction process by using the surrogate constraint algorithm with random constraint selection. The described algorithm considers a small number of constraints at a time, which makes it suitable for serial implementation.

High‐loop‐delay sixth‐order bandpass continuous‐time sigma–delta modulators

This study focuses on the design of high-loop-delay modulators for parallel sigma-delta conversion. Parallel converters, allowing a global low oversampling ratio, consist of several bandpass modulators with adjacent central frequencies. To ensure the global performance, the noise transfer function (NTF) of each modulator must be adjusted regarding its central frequency. In this thematic a new topology of sixth-order modulators based on weighted-feedforward techniques is developed. This topology offers an adequate control of the NTF at each central frequency by simple means. Additive signal paths are moreover proposed to obtain an auto-filtering signal transfer function. An optimisation method is also developed to calculate the optimised coefficients of the modulators at different central frequencies. The main concerns are improving the stability and reducing the sensitivity of the continuous-time circuit to analogue imperfections. This is essential for parallel conversion since, in each channel, the modulator works at a central frequency which differs from the fourth of the sampling frequency. The performance of the optimised modulator is compared with its discrete-time counterpart with good argument.

Superchannel transmission system based on multi-channel equalization

We proposed a new method for superchannel transmission based on the newly proposed multi-channel equalization technique. This method allows us to realize tight channel spacing (equal to the baud rate) without using frequency-locked lasers and complex spectral shaping techniques at the transmitter. The inter-channel interference originated from the tight channel spacing is removed at the receiver by joint equalization of multiple adjacent channels. When the channel spacing is equal to the baud rate, our simulation results show that, with conventional oversample ratio (2 samples per symbol), realistic laser frequency offset and laser linewidth, the proposed multi-channel-equalization based method can achieve better performance than the traditional method using spectral shaping plus single channel equalization, although at the expense of a moderate increase in DSP complexity. The paper also gives a simple method to process the data after conventional chromatic dispersion compensation, which enables subsequent multi-channel equalization for long-haul transmissions.

ERRATUM: "AN ENERGY EFFICIENT SECOND-ORDER ΣΔ MODULATOR BASED ON THE POWER AND DELAY OPTIMIZATION OF CBSC IIR FILTER"

In this paper a second-order low distortion Sigma-Delta Modulator (ΣΔM) with utilization of Comparator-Based Switched-Capacitor (CBSC)-based IIR filter, is explored. The advantages of this new structure are justified by the reduction of power and area. For this purpose IIR filter block can be made with single CBSC gain stage that has the same accuracy and performance of second-order filter with two Op-amps. The design of CBSC gain stages is intended to minimize the power consumption, and maximize Modulator performance. As shown in the simulation result, for a 20-KHz signal bandwidth, the modulator achieves a dynamic range of 70.2 dB and a peak signal-to-noise and distortion ratio (SNDR) of 68 dB with an over-sampling ratio of 64. In addition it consumes only 198 μW from a 1.8-V power supply at 2.56 MS/s.

An 80-dB DR, 7.2-MHz Bandwidth Single Opamp Biquad Based CT $\Delta \Sigma$ Modulator Dissipating 13.7-mW

A novel low power compact loop filter using a single amplifier biquad (SAB) network is presented for continuous-time (CT) delta-sigma (ΔΣ) modulators. This new technique reduces power consumption and die area by minimizing the number of active elements and simplifying the modulator topology. The new SAB network has a transfer function (TF) zero, which implements a local feedforward (FF) path in system-level diagram. By having a local FF branch embedded in the SAB network, the FF branches to the summing block in the SAB based feedforward modulator topology is reduced to half the number of FF branches in the conventional topology. Consequently, the SAB based modulator utilizes a switch-capacitor (SC) adder replacing the commonly used CT adder and the sample & hold blocks in the conventional architecture. The SAB based loop filter with reduced FF branches simplifies the design and implementation of the high-order continuous-time ΔΣ modulator. The proposed loop filter is a general filter, which can be used for both high and low oversampling ratios (OSRs). A 4th-order low pass continuous-time ΔΣ modulator is designed and implemented in 130 nm process to confirm the effectiveness of the proposed techniques. Within a 7.2 MHz signal bandwidth, the measured dynamic range and SFDR of this prototype IC are 80 dB and 83.1 dB, respectively, and the total power consumption of 13.7 mW.

AN ENERGY EFFICIENT SECOND-ORDER ΣΔ MODULATOR BASED ON THE POWER AND DELAY OPTIMIZATION OF CBSC IIR FILTER

In this paper a second-order low distortion Sigma-Delta Modulator (ΣΔM) with utilization of Comparator-Based Switched-Capacitor (CBSC)-based IIR filter, is explored. The advantages of this new structure are justified by the reduction of power and area. For this purpose IIR filter block can be made with single CBSC gain stage that has the same accuracy and performance of second-order filter with two Op-amps. The design of CBSC gain stages is intended to minimize the power consumption, and maximize Modulator performance. As shown in the simulation result, for a 20-KHz signal bandwidth, the modulator achieves a dynamic range of 70.2 dB and a peak signal-to-noise and distortion ratio (SNDR) of 68 dB with an over-sampling ratio of 64. In addition it consumes only 198 μW from a 1.8-V power supply at 2.56 MS/s.

A Performance Prediction Method with an Equation-Based Behavioral Model for a Single-Bit Single-Loop Sigma-Delta Modulator

An equation-based behavioral model has been developed to predict the real performance of a single–loop single-bit Sigma Delta Modulator (SDM). By using this prediction flow, not only can the circuit specifications be acquired, including the gain, bandwidth, slew rate of the OPAMPs, and the capacitor value in the switched-capacitor circuits, but the real performance of the SDM can also be predicted. The switched-capacitor circuits according to the required circuit specifications are employed to design a fourth-order feed-forward (FF) SDM with an over-sampling ratio (OSR) of 64 and a bandwidth of 10kHz using a TSMC 0.35µm CMOS process. The measurement results reveal that the SDM with an input frequency of 2.5kHz and a supply voltage of 3.3V can achieve a dynamic range of 90dB and a spurious-free dynamic range (SFDR) of 85dB under the signal bandwidth of 10kHz and a sampling frequency of 1.28MHz, respectively. The precision of the equation-based behavioral model has been validated by experimental measurements, and its inaccuracy is less than 4%.

A Digital Readout IC with Digital Offset Canceller for Capacitive Sensors

A digital readout IC for capacitive sensors is presented. Digital capacitance readout circuits suffer from static capacitance of sensors, especially single-ended sensors, and require large passive elements to cancel such DC offset signal. For this reason, to maximize a dynamic range with a small die area, the proposed circuit features digital filters having a coarse and fine compensation steps. Moreover, by employing switched-capacitor circuit for the front-end, correlated double sampling (CDS) technique can be adopted to minimize low-frequency device noise. The proposed circuit targeted 8-㎑ signal bandwidth and oversampling ratio (OSR) of 64, thus a 3 rd -order ΔΣ modulator operating at 1 ㎒ was used for pulse-density-modulated (PDM) output. The proposed IC was designed in a 0.18-㎛ CMOS mixed-mode process, and occupied 0.86 × 1.33 ㎟. The measurement results shows suppressed DC power under about -30 ㏈FS with minimized device flicker noise.

Design and Assessment of a 6 ps-Resolution Time-to-Digital Converter With 5 MGy Gamma-Dose Tolerance for LIDAR Application

Time-to-Digital Converters (TDCs) are key building blocks in time-based mixed-signal systems, used for the digitization of analog signals in time domain. A short survey on state-of-the-art TDCs is given. A novel multi-stage noise-shaping (MASH) delta-sigma $(\Delta\Sigma)$ TDC structure is proposed for applications in continuous-time pulsed time-of-flight (TOF) rangefinders for nuclear reactor remote sensing, which requires both high resolution and multi MGy gamma-dose radiation tolerance. The converter, implemented in 0.13 $\mu{\rm m}$ , achieves a time resolution of 5.6 ps and an ENOB of 11 bits, when the oversampling ratio (OSR) is 250. The TDC core consumes only 1.7 mW and occupies an area of 0.11 ${\rm mm}^{2}$ . Owing to the usage of circuit level radiation hardened-by-design techniques, such as passive RC oscillators and constant- $g_{m}$ biasing, the TDC exhibits enhanced radiation tolerance. At a low dose rate of 1.2 kGy/h, the frequency of the counting clock in the TDC remains constant up to at least 160 kGy. Even after a total dose of 3.4 MGy at a high dose rate of 30 kGy/h, the TDC still achieves a time resolution of 10.5 ps with an OSR of 250.

Verification Decoding of High-Rate LDPC Codes With Applications in Compressed Sensing

This paper considers the performance of (j, k)-regular low-density parity-check (LDPC) codes with message-passing (MP) decoding algorithms in the high-rate regime. In particular, we derive the high-rate scaling law for MP decoding of LDPC codes on the binary erasure channel (BEC) and the q-ary symmetric channel (q-SC). For the BEC and a fixed j, the density evolution (DE) threshold of iterative decoding scales like Θ(k <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> ) and the critical stopping ratio scales like Θ(k <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-j/(j-2)</sup> ). For the q-SC and a fixed j, the DE threshold of verification decoding depends on the details of the decoder and scales like Θ(k <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> ) for one decoder. Using the fact that coding over large finite alphabets is very similar to coding over the real numbers, the analysis of verification decoding is also extended to the compressed sensing (CS) of strictly sparse signals. A DE-based approach is used to analyze the CS systems with randomized-reconstruction guarantees. This leads to the result that strictly sparse signals can be reconstructed efficiently with high probability using a constant oversampling ratio (i.e., when the number of measurements scales linearly with the sparsity of the signal). A stopping-set-based approach is also used to get stronger (e.g., uniform-in-probability) reconstruction guarantees.

RF-to-Baseband Digitization in 40 nm CMOS With RF Bandpass $\Delta\Sigma$ Modulator and Polyphase Decimation Filter

A fourth-order continuous-time RF bandpass ΔΣ ADC has been fabricated in 40 nm CMOS for <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fs</i> /4 operation around a 2.22 GHz central frequency. A complete system has been implemented on the test chip including the ADC core, the fractional-N PLL with clock generation network, and the digital decimation filters and downconversion (DFD). The quantizers of the ADC are six times interleaved enabling a polyphase structure for the DFD and relaxing clock frequency requirements. This quantization scheme realizes a sampling rate of 8.88 GS/s which is the highest sampling speed for RF bandpass ΔΣ ADCs reported in standard CMOS to date enabling high oversampling ratios for RF digitization without compromising power-efficient implementation of the DFD. Measurements show that the ADC achieves a dynamic range of 48 dB in a band of 80 MHz with an IIP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> of 1 dBm.

A 250 mV 7.5 μW 61 dB SNDR SC ΔΣ Modulator Using Near-Threshold-Voltage-Biased Inverter Amplifiers in 130 nm CMOS

An ultra-low voltage switched-capacitor (SC) ΔΣ converter running at a record low supply voltage of only 250 mV is introduced. System level aspects are discussed and special circuit techniques described, that enable robust operation at such a low supply voltage. Using a SC biasing approach, inverter-based integrators are realized with overdrives close to the transistor threshold voltage Vth while compensating for process, voltage and temperature (PVT) variation. Biasing voltages are generated on-chip using a novel level shifting circuit, that overcomes headroom limitations due to saturation voltage Vsat. With an oversampling ratio (OSR) of 70 and a sampling frequency (fS) of 1.4 MHz at 250 mV power supply the converter achieves 61 dB SNDR in 10 kHz bandwidth while consuming a total power of 7.5 μW.

A High-Performance Mash Fourth-Order Sigma-Delta Modulator

This paper reports on a system level design and analysis of a mash fourth-order sigma-delta (ΣΔ) modulator. Compared with a high-order single-loop ΣΔ modulator (ΣΔM), there’s no need to consider about the system stability of a mash ΣΔM, which has the advantages of better signal to quantization noise ratio (SQNR). System level simulation results indicate that the SQNR is 122.0 dB, and the effective number of bits (ENOB) is 19.97 bits when the over sampling ratio (OSR) is 128.

The Design of CIFF Structure Three-Order Switched-Capacitor Sigma-Delta Modulator

This paper presents the design and implementation of a single-loop three-order switched-capacitor sigma-delta modulator(SDM) with a standard 0.18um CMOS technology. A current optimization technique is utilized in proposed design to reduce the power of operational transconductance amplifier(OTA).Using a chain of Integrators with weighted feed-forward summation(CIFF) structure and optimized single-stage class-A OTA with positive feed-back to minimize the power consumption. The SDM has been presented with an over-sampling ratio of 128,clock frequency 6.144MHz,24kHz band- width, and achieves a peak SNR of 100dB,103dB dynamic range. The whole circuits consume 2.87mW from a single 1.8V supply voltage.

Design of A high performance low-power consumption discrete time Second order Sigma-Delta modulator used for Analog to Digital Converter

This paper presents the design and simulations results of a switched-capacitor discrete time Second order Sigma-Delta modulator used for a resolution of 14 bits Sigma-Delta analog to digital converter. The use of operational amplifier is necessary for low power consumption, it is designed to provide large bandwidth and moderate DC gain. With 0.35µm CMOS technology, the S? modulator achieves 86 dB dynamic range, and 85 dB signal to noise ratio (SNR) over an 80 KHz signal bandwidth with an oversampling ratio (OSR) of 88, while dissipating 9.8mW at ±1.5V supply voltage.

Dynamic OSR dithered sigma-delta modulation in solid state light dimming

SUMMARY Pulse width modulation (PWM) is the most common way to control switching regulation and digital dimming. This paper presents a way to implement digital dimming by means of a dithered sigma–delta modulator with dynamic oversampling ratio. The system has been modeled in SystemC-WMS and implemented in a board using a commercial microcontroller. Simulation results show conducted electromagnetic interference reduction compared to PWM and flickering reduction with respect to classic sigma-delta modulation. Copyright © 2011 John Wiley & Sons, Ltd.