Abstract
This paper presents the design and simulations results of a switched-capacitor discrete time Second order Sigma-Delta modulator used for a resolution of 14 bits Sigma-Delta analog to digital converter. The use of operational amplifier is necessary for low power consumption, it is designed to provide large bandwidth and moderate DC gain. With 0.35µm CMOS technology, the S? modulator achieves 86 dB dynamic range, and 85 dB signal to noise ratio (SNR) over an 80 KHz signal bandwidth with an oversampling ratio (OSR) of 88, while dissipating 9.8mW at ±1.5V supply voltage.
Highlights
Analog to digital converters (ADC) with high resolution are widely used in the areas of instrumentation, measurement, telecommunications, digital signal processing, consumer electronics, etc
With the advancements in the Very Large Scale Integration (VLSI) technologies, the focus is shifted on oversampling and ΔΣ converters for applications requiring high precision analog-to digital conversion with narrow bandwidth [1, 2, 3, 4]
They are preferred because of their inherent relaxed sensitivity to analog circuit errors and reduced analog processing as compared to other analog-to-digital conversion techniques. These advantages come at the expense of relatively large amount of digital processing and the working of the majorpart of circuit at a clock rate which is much higher than the analog-to-digital conversion rate
Summary
Analog to digital converters (ADC) with high resolution are widely used in the areas of instrumentation, measurement, telecommunications, digital signal processing, consumer electronics, etc. With the advancements in the Very Large Scale Integration (VLSI) technologies, the focus is shifted on oversampling and ΔΣ converters for applications requiring high precision analog-to digital conversion with narrow bandwidth [1, 2, 3, 4]. They are preferred because of their inherent relaxed sensitivity to analog circuit errors and reduced analog processing as compared to other analog-to-digital conversion techniques.
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