Oversampling Ratio Research Articles

A wideband CMOS sigma-delta modulator with incremental data weighted averaging

A low-complexity high-speed circuit is proposed for the implementation of an incremental data weighted averaging (IDWA) technique used for reducing digital-to-analog converter (DAC) noise due to component mismatches. IDWA can achieve very good performance even when it is used with a low oversampling ratio (OSR), which reduces demands on circuit speed and power consumption. Therefore, the IDWA is highly suitable for wideband, low-power and small-area sigma-delta modulator (SDM) implementation. Incorporating the IDWA technique, a fourth-order feedforward (FF) SDM with an OSR of 12 and a 4-bit internal quantizer is implemented with a 2.5-V 0.25-/spl mu/m CMOS process. Measurement results show that the SDM operating from a 2.5-V supply voltage can achieve respective dynamic ranges (DRs) of 84/80 dB and spurious-free dynamic ranges (SFDRs) of 90/85 dB with signal bandwidths of 1.25/2 MHz at sampling frequencies of 30/48 MHz. The power dissipation is less than 105 mW and the active area is 2.6 mm/sup 2/. Wider bandwidth, lower OSR, less power, and lower supply voltage are achieved compared with two recently published 3.3-V/3-V CMOS wideband SDMs with comparable SNDR performance.

Interpolation filter and method for switching between integer and fractional interpolation rates

A voice or data transmission system and specifically an interpolation filter used within the transmission system is provided for producing either fractional or integer interpolation ratios. The digital signal resulting from the interpolation filter has a relatively high signal to noise ratio whenever fractional interpolation is needed. The interpolation filter includes multiple stages coupled in series, and an integer interpolation branch switched in parallel with a fractional interpolation branch. A controller determines whether the integer or fractional interpolation ratio is needed based on maintaining a fixed oversampling data rate from the interpolation filter given a changing incoming sampling rate. If the incoming sampling rate should require fractional interpolation, then a branch implementing fractional interpolation ratio is used in lieu of the integer interpolation ratio. A comb filter is preferably introduced within the fractional interpolation branch to attenuate imaging tones within the baseband of interest. An interpolation rate change switch used by the comb filter beneficially moves the imaging tones further away from the baseband so that minimum imaging noise is introduced within the baseband by the fractional oversampling ratio.

Blind identifiability of IIR systems

It is shown that, with no prior information, a necessary and sufficient condition for an nth order IIR system to be blindly identifiable is that the over-sampling ratio p⩾ n+1.

Analog-to-digital converter testing method based on segmented correlations

The high sampling rates of superconducting analog-to-digital (A/D) converters complicate testing since the output data rates often exceed the capacity of the interface to room-temperature electronics. Capturing the data with an on-chip shift register allows low speed interfacing, but integration limits of current Josephson technology make such an approach impractical for oversampling converters, as the shift register length must be much larger than the oversampling ratio (OSR). In this paper, we describe a scheme in which two segments of the output data stream are captured with a pair of shift registers, whose lengths can be less than the OSR. The number of clock cycles skipped between acquiring the two segments is set by an on-chip programmable counter (from 0 to N, where N is much larger than the OSR). Cross-correlation of the two segments provides an estimate of the output autocorrelation function R[n], over a narrow range of n. By reprogramming the counter, other sections of R[n] can be estimated through successive measurements, allowing assembly of the entire function R[n] (up to n=N). Fourier transformation of R[n] yields a spectrum with the frequency resolution of an N-point FFT. Both low-pass and bandpass A/D converters can be studied with the method.

Two-step quantization in multibit ΔΣ modulators

An architecture to simplify the circuit implementation of the internal analog-to-digital (A/D) converter in a /spl Delta//spl Sigma/ modulator is proposed. The architecture is based on dividing the A/D conversion into two time steps, which makes the internal quantization feasible with much higher resolution than with conventional solutions. Furthermore, the time steps are interleaved so that the resolution improvement is achieved without sacrificing the speed. It is shown, with a linearized model, that the order of the noise shaping is increased by one with respect to the coarse quantization error made during the first step. For a high oversampling ratio, the coarse quantization error made in the first step is easily suppressed to an insignificant level due to the one order higher noise shaping. Depending on the partitioning of the bits between the conversion steps, the coarse error will dominate below a certain oversampling ratio. However, it is shown that the technique can be extended to more than one order higher noise shaping, making it useful for low oversampling ratios as well.

14-bit 2.2-MS/s sigma-delta ADC's

This paper presents the design and test results of a fourth-order and sixth-order 14-bit 2.2-MS/s sigma-delta analog-to-digital converter (ADC). The analog modulator and digital decimator sections were implemented in a 0.35 /spl mu/m CMOS double-poly triple-level metal 3.3-V process. The design objective for these ADC's was to achieve 85 dB signal-to-noise distortion ratio (SNDR) with less than 200 mW power dissipation. Both modulators employ a cascade sigma-delta topology. The fourth-order modulator consists of two cascaded second-order stages which include 1-bit and 5-bit quantizers, respectively. The sixth-order modulator has a 2-2-2 cascade structure and 1-bit quantizer at the end of each stage. An oversampling ratio of 24 was selected to give the best SNDR and power consumption with realizable gain-matching requirements between the analog and digital sections.

Blind system identification and channel equalization of IIR systems without statistical information

A novel approach is proposed to blindly identify an unknown IIR system. The approach is based on faster sampling at the system output and requires neither a priori statistical information on the unknown input nor training signals. The methods presented are linear in the parameters of the unknown system so that many standard recursive algorithms can be readily applied. It is also shown in the paper that under a generic condition, any finite-order IIR system is identifiable, provided the oversampling ratio is appropriately chosen.

Heterodyning technique to improve performance of delta-sigma-based beamformers

Delta-sigma (DeltaSigma) modulators can implement a simpler digital ultrasound beamformer than can traditional architectures based on multi-bit analog-to-digital converters (A/D). The signal-to-noise ratio (SNR) of the DeltaSigma modulators, however, suffers from limited oversampling ratios. To improve the SNR of each channel, a mixing signal heterodynes narrowband signals to lower frequencies where the baseband DeltaSigma modulator performs better. Noise figure analyses are presented that illustrate the effectiveness of this technique in improving noise performance. Also, spectral Doppler and color flow simulations are presented that realistically emulate a 32 channel oversampled beamformer and compare these results with traditional and ideal systems.

A 13-bit, 2.2-MS/s, 55-mW multibit cascade ΣΔ modulator in CMOS 0.7-μm single-poly technology

This paper presents a CMOS 0.7-/spl mu/m /spl Sigma//spl Delta/ modulator IC that achieves 13-bit dynamic range at 2.2 MS/s with an oversampling ratio of 16. It uses fully differential switched-capacitor circuits with a clock frequency of 35.2 MHz, and has a power consumption of 55 mW. Such a low oversampling ratio has been achieved through the combined usage of fourth-order filtering and multibit quantization. To guarantee stable operation for any input signal and/or initial condition, the fourth order shaping function has been realized using a cascade architecture with three stages; the first stage is a second-order modulator, while the others are first-order modulators-referred to as a 2-1-1/sub mb/ architecture. The quantizer of the last stage is 3 bits, while the other quantizers are single bit. The modulator architecture and coefficients have been optimized for reduced sensitivity to the errors in the 3-bit quantization process. Specifically, the 3-bit digital-to-analog converter tolerates 2.8% FS nonlinearity without significant degradation of the modulator performance. This makes the use of digital calibration unnecessary, which is a key point for reduced power consumption. We show that, for a given oversampling ratio and in the presence of 0.5% mismatch, the proposed modulator obtains a larger signal-to-noise-plus-distortion ratio than previous multibit cascade architectures. On the other hand, as compared to a 2.1.1/sub single-bit/ modulator previously designed for a mixed-signal asymmetrical digital subscriber line modem in the same technology, the modulator in this paper obtains one more bit resolution, enhances the operating frequency by a factor of two, and reduces the power consumption by a factor of four.

Delta-sigma modulator with large OSR using the one-hot residue number system

A digital delta-sigma modulator using the one-hot residue number system (OHRNS) is presented. It exhibits a large oversampling ratio (OSR) in comparison with equivalent binary designs. Its second-order architecture employs a two-stage cascade structure with two-level internal and four-level output quantization. It is intended for use in a high-resolution interpolative digital-to analog converter. Analytical estimates show a significant improvement in OSR and latency over binary-number system-based designs. These benefits are made possible by the use of the (OHRNS), which allows addition and multiplication to be performed equally quickly and simply, using barrel shifters and signal transposition. An application specific integrated circuit (ASIC) implementation of the design is also presented in a 2-/spl mu/m CMOS technology.

An improved technique for reducing baseband tones in sigma-delta modulators employing data weighted averaging algorithm without adding dither

The data weighted averaging (DWA) algorithm used in multibit sigma-delta modulators (SDM) is troubled by baseband tones resulting from component mismatch of the SDM's internal multi-bit digital-to-analog converter (DAC). In this paper, we analyze DAC baseband tones and find them closely correlated to the number of unit elements used in the DAC. An improved technique is proposed for shifting the DAC tones away from the baseband without adding dither. For third-order sigma-delta modulators with an oversampling ratio (OSR) of 64 and either a nine-level or eight-level internal DAC with 0.5%-2% random component mismatches, simulation reveals that the DWA algorithm with the proposed technique can achieve nearly perfect first-order DAC noise shaping in the baseband and, on the average, 12 dB improved signal-to-(noise and distortion) ratio and 20 dB improved in-band distortion.

Tight Weyl-Heisenberg frames in l/sup 2/(Z)

Tight Weyl-Heisenberg frames in l/sup 2/(Z) are the tool for short-time Fourier analysis in discrete time. They are closely related to paraunitary modulated filter banks and are studied here using techniques of the filter bank theory. Good resolution of short-time Fourier analysis in the joint time-frequency plane is not attainable unless some redundancy is introduced. That is the reason for considering overcomplete Weyl-Heisenberg expansions. The main result of this correspondence is a complete parameterization of finite length tight Weyl-Heisenberg frames in l/sup 2/(Z) with arbitrary rational oversampling ratios. This parameterization follows from a factorization of polyphase matrices of paraunitary modulated filter banks, which is introduced first.

A simulator core for charge-pump PLLs

Three techniques are introduced to enhance the simulation speed of communication systems including a charge-pump phase-locked loop. First, a technique using exact explicit solutions of differential equations is extended to nonuniformly sampled circuits. This allows arbitrarily large time and voltage steps in an event-driven simulator without introducing numerical errors. Then, event prediction using mathematical limits enables large time steps and unlimited accuracy. Finally, an interpolator is combined with delay-partitioning to reduce the required oversampling rate. High accuracy is demonstrated with as low as four events per cycle of the system clock and an oversampling ratio of 3.

A new design and performance -test strategy for sigma-delta modulators

The paper proposes a new approach to sigma-delta modulator design based on linear and non-linear control theories combined with a number of digital signal processing techniques. The limitations single-stage high-order designs are analysed as a compatibility problem between the linear filtering and non-linear quantiser requirements. The comnplexity versus performance-improvements of other strategies are also discussed. In addition to the new approach to component-compatibility analysis, the paper proposes a more rigorous analyses of the system performance by using, for the first time, groups of harmonic-rich test signals. Based on this new approach and the extensive analysis of how jointly and severally the linear and non-linear parameters influence the modulator's performance, a new design strategy is proposed and results demonstrated on a single-stage second-order modulator. The results are compared with those of an already-published second-order design for low over-sampling ratio of 64. It is shown that under the same conditions the new modulator exhibits a significantly improved signial-to-noise-ratio response' over a wide dynamic range of input signals. Finally, the conclusion discusses how this approach can be extendecl to other designs as well as used as a framework to completeyl new adaptive strategies.

Design techniques for high-resolution current-mode sigma-delta modulators

This paper describes techniques for the design of high-resolution oversampling analog-to-digital converters based on current memories. A key point is the reduction of nonlinearities, in particular those introduced by the current switches. A current-memory cell with very high precision and linearity has been designed and used in an experimental third-order /spl Sigma/-/spl delta/ modulator in a 0.8-/spl mu/m digital CMOS process. A linearity of better than 14 b and a maximum signal-to-noise+distortion ratio (SNDR) of 80 dB has been measured for an oversampling ratio (OSR) of 64.

A 1.8-V digital-audio sigma-delta modulator in 0.8-μm CMOS

Oversampling techniques based on sigma-delta (/spl Sigma//spl Delta/) modulation offer numerous advantages for the realization of high-resolution analog-to-digital (A/D) converters in low-voltage environment. This paper examines the design and implementation of a CMOS /spl Sigma//spl Delta/ modulator for digital-audio A/D conversion that operates from a single 1.8-V power supply. A cascaded modulator that maintains a large full-scale input range while avoiding signal clipping at internal nodes is introduced. The experimental modulator has been designed with fully differential switched-capacitor integrators employing different input and output common-mode levels and boosted clock drivers in order to facilitate low voltage operation. Precise control of common-mode levels, high power supply noise rejection, and low power dissipation are obtained through the use of two-stage, class A/AB operational amplifiers. At a sampling rate of 4 MHz and an oversampling ratio of 80, an implementation of the modulator in a 0.8-/spl mu/m CMOS technology with metal-to-polycide capacitors and NMOS and PMOS threshold voltages of +0.65 V and -0.75 V, respectively, achieves a dynamic range of 99 dB at a Nyquist conversion rate of 50 kHz. The modulator can operate from supply voltages ranging from 1.5-2.5 V, occupies an active area of 1.5 mm/sup 2/, and dissipates 2.5 mW from a 1.8-V supply.

Poly-phase sigma-delta modulation

A new circuit is described for the implementation of analog sigma-delta modulation. It is based upon the use of a poly-phase sampler with the aim of obtaining high over-sampling ratios at low clock frequencies. A detailed analysis of second-order systems is made to predict its performance. The basic modeling comprises the incorporation of sampling noise within limit cycle oscillations of the modulator. It is shown that the polyphase sigma-delta modulator can be conceived as an internally sampled asynchronous sigma-delta modulator. The theoretical model presupposes a low limit cycle frequency as compared with the effective sampling frequency. In spite of the fact that this condition is not met in the extreme of conventional single-phase sigma-delta modulation, the theoretical result obtained for this special case is close to the result obtained from the conventional sampled data model. Poly-phase sigma-delta modulation may therefore be regarded as a generalization of conventional single-phase sigma-delta modulation. The results of the theory are illustrated by simulation results of a practical design example.

A second-order double-sampled delta-sigma modulator using individual-level averaging

A second-order double-sampled delta-sigma modulator is described. It uses all individual-level-averaging switching scheme to convert capacitor mismatch into high-pass noise. With a sampling rate of 25 MHz and an oversampling ratio of 128, the maximum measured signal-to-noise-and-distortion ratio is 82.2 dB, and the total harmonic distortion is -91.0 dB when the input is 2.5 dB below full scale. The modulator is fully differential, occupies 3.75 mm/sup 2/ in a 1.2-/spl mu/m CMOS process, and dissipates 25.9 mW (10.2 mW analog and 15.7 mW digital).

A low oversampling ratio 14-b 500-kHz ΔΣ ADC with a self-calibrated multibit DAC

Delta-sigma (/spl Delta//spl Sigma/) analog-to-digital converters (ADC's) rely on oversampling to achieve high-resolution. By applying multibit quantization to overcome stability limitations, a circuit topology with greatly reduced oversampling requirements is developed. A 14-bit 500-kHz /spl Delta//spl Sigma/ ADC is described that uses an oversampling ratio of only 16. A fourth-order embedded modulator, four-bit quantizer, and self-calibrated digital-to-analog converter (DAC) are used to achieve this performance. Although the high-order embedded architecture was previously thought to be unstable, it is shown that with proper design, a robust system can be obtained. Circuit design and implementation in a 1.2-/spl mu/m CMOS process are presented. Experimental results give a dynamic range of 84 dB with a sampling rate of 8 MHz and oversampling ratio of 16. This is the lowest oversampling ratio for this resolution and bandwidth achieved to date.

A second-order double-sampled delta-sigma modulator using additive-error switching

A second-order double-sampled delta-sigma modulator is described. It uses an additive-error switching scheme to convert capacitor mismatch into an additive out-of-band tone that can be removed by a digital filter. With a sampling rate of 5 MHz and an oversampling ratio of 256, the maximum measured signal-to-noise-and-distortion ratio (SNDR) is 86.3 dB, and the total harmonic distortion is -88.7 dB when the input is 2 dB below full scale. The modulator is fully differential, occupies 5 mm/sup 2/, and dissipates 13 mW.