A 96 dB DR Second-Order CIFF Delta-Sigma Modulator with Rail-to-Rail Input Voltage Range

Abstract

A second-order delta-sigma modulator (DSM) is proposed for readout integrated circuits of sensor applications requiring a small area and low-power consumption. The proposed second-order CIFF DSM with the architecture of cascaded-of-integrator feedforward (CIFF) basically consists of two integrators, a 3-bit quantizer, data-weighted averaging (DWA) circuit, and clock generator. The use of the 3-bit quantizer instead of the single-bit quantizer reduces the size of the feedback capacitor in the first integrator. The 3-bit quantizer is designed based on a successive approximation register analog-to-digital converter for small area and low power implementation. Furthermore, the proposed second-order CIFF DSM has a single supply without an additional reference driver while having a wide analog input voltage range with rail to rail. The proposed second-order CIFF DSM, implemented using a 130 nm 1-poly 6-metal CMOS process with a supply of 1.5 V, has an area of 0.096 mm2. It has a sampling frequency of 500 kHz for the implementation of an input bandwidth of 2 kHz and an oversampling ratio of 125. The measured peak signal-to-noise and distortion ratio is approximately 90 dB when the differential analog input signal has a frequency of 353 Hz and an amplitude of 1.2 Vpp. The measured dynamic range is approximately 96.3 dB.