A Time-Domain Reconfigurable Second-Order Noise Shaping ADC With Single Fan-Out Gated Delay Cells

Abstract

This brief proposes a time-domain second-order noise shaping analog-to-digital converter (ADC). It employs a voltage-to-time converter (VTC) in tandem with a second-order noise shaping time-to-digital converter (TDC), which realizes the goal of reducing the power consumption and accommodating different resolutions by configuring locations of poles of the transfer function. Note that the time-register constructed TDC, which performs the signal processing function in the time domain, is implemented with digital cells thoroughly. In this way, the proposed architecture can be more friendly to the increasingly scaled process. The reconfigurable architecture enables to obtain the target signal-to-noise-and-distortion ratio (SNDR) with decreased oversampling ratio (OSR), which improves energy efficiency relatively. In addition, compared with the conventional CMOS gated delay cell, the proposed single fan-out (SFO) gated delay cell is featured with lower power dissipation and shorter delaying time. The prototype is implemented in a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\bm\mu$</tex-math> </inline-formula> m CMOS technology to demonstrate the validity of this proposed time-domain ADC. It achieves 64.5-, 56.1-, and 51.2-dB SNDR in 0.025-, 0.05-, and 0.1-MHz bandwidth on conditions of the OSR being 200, 100, and 50, respectively.