Abstract
This paper presents a 4th-order interstage gain error shaping (GES) technique in pipeline successive approximation register (SAR) analog-to-digital converters (ADCs), which can substantially suppress the in-band quantization leakage error induced by the gain error. It is realized by simply arranging a low-order cascaded-integrator feed-forward (CIFF) structure in the first stage. In addition, the comparator noise and quantization error can be shaped together with the gain error in the proposed architecture. Verified by simulation in a 28-nm CMOS process, the prototype achieves a signal-to-noise-and-distortion ratio (SNDR) of 77.8 dB over 25-MHz bandwidth (BW) with oversampling ratio (OSR) of 8. Within a gain error range of −33 % to +33 %, the SNDR of the ADC deviates less than 3 dB. Under a 1 V supply voltage, the ADC consumes 3.75 mW and exhibits a Scherier figure of merit (FoMs) of 176 dB.
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