Abstract
Noise-Shaping (NS) Successive-Approximation (SAR) Analog-to-Digital Converters (ADCs) are one of the most heavily researched ADC topologies in recent years. This high attention is attributed to the advantages of the NS SAR architecture that combines the merits of ΣΔ and SAR converters. However, the implementation of the NS SAR loop-filter in a passive or an active form imposes challenging tradeoffs among power dissipation, adequacy for scaling with technology, performance, and robustness against process-voltage-temperature (PVT) variations. In this work, a NS SAR ADC realization, based on inverter-based amplification, is proposed that alleviates these design challenges. The proposed implementation is used to design two ADCs in 28 nm CMOS technology to demonstrate its effectiveness. The first ADC employs an active loop-filter and achieves a signal-to-noise-plus-distortion (SNDR) of 62.9 dB, at a sampling frequency of 90 MHz, and an oversampling ratio (OSR) of 4, while consuming 0.59 mW from a 0.9 V supply. The second ADC has a passive loop-filter and provides 61 dB of SNDR for the same OSR and sampling frequency, with 0.58 mW power dissipation.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.