Noise-shaping Successive Approximation Register Research Articles

A Review on Fundamentals of Noise-Shaping SAR ADCs and Design Considerations

A general overview of Noise-Shaping Successive Approximation Register (SAR) analog-to-digital converters is provided, encompassing the fundamentals, operational principles, and key architectures of Noise-Shaping SAR (NS SAR). Key challenges, including inherent errors in processing circuits, are examined, along with current advancements in architecture design. Various issues, such as loop filter optimization, implementation methods, and DAC network element mismatches, are explored, along with considerations for voltage converter performance. The design of dynamic comparators is examined, highlighting their critical role in the SAR ADC architecture. Various architectures of dynamic comparators are extensively explored, including optimization techniques, performance considerations, and emerging trends. Finally, emerging trends and future challenges in the field are discussed.

A 3.07 mW 30 MHz-BW 73.2 dB-SNDR Time- Interleaved Noise-Shaping SAR ADC With Self-Coupling Second-Order Error-Feedforward

A noise-shaping successive approximation register (NS-SAR) ADC combines the merits of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta $</tex-math> </inline-formula> - <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Sigma $</tex-math> </inline-formula> and SAR ADC, transforming it into an emerging ADC architecture to reach high resolution with good power efficiency. The single-channel NS-SAR with high resolution, however, suffers from bandwidth (BW) limitations. The time-interleaved (TI) NS-SAR mitigates the speed bottleneck but faces challenges in obtaining high resolution and BW simultaneously due to the lack of a sharp noise transfer function (NTF). This article presents a calibration-free two-channel TI-NS-SAR with an aggressive second-order NTF for high resolution. Based on a one-time error feedback (FB) at midway, we propose a second-order error-feedforward (FF) to enhance the noise-shaping (NS) effect further meanwhile avoiding the excessive NTF peaking and dynamic range (DR) loss. A dynamic residue amplifier shared between two channels lowers the offset, which reduces the redundant bit to only one bit, thus improving the efficiency of SAR conversion. Fabricated in a 28 nm CMOS with 1 V supply, the prototype achieves 73.2 dB-signal-to-noise-and-distortion-ratio (SNDR) over 30 MHz-BW when operating at 330 MHz. It consumes 3.07 mW and exhibits a Schreier FoM (FoMs) of 173.1 dB.

A Data Weight Averaging-Inspired Digital Calibration Method for a 10-Bit Noise-Shaping Successive Approximation Register

This paper presents a digital calibration method for a 10-bit noise-shaping Successive Approximation Register Analog to Digital Converter (SAR ADC). The proposed calibration method is inspired by its Data Weight Averaging (DWA) counterpart, but stays static, while achieving a similar Integral Nonlinearity (INL) and 1.3 dB better Signal-to-Noise Ratio (SNR) in measurements without oversampling. This advantage in SNR holds until an Oversampling Ratio (OSR) of 2 for the proposed method, which also saves 50 % power. At a 1.2 V power supply, the ADC consumes a power of 70 µW at a conversion rate of 50 kHz. Fabricated using 55 nm Complementary Metal Oxide Semiconductor (CMOS) Metal-Oxide-Metal Capacitor (MOMCAP) technology, it occupies an active area of 370 µm × 350 µm, when achieving an INL of 0.3 Least Significant Bit (LSB) and an SNR of 66.9 dB at an OSR of 8.

A 77.3-dB SNDR 62.5-kHz Bandwidth Continuous-Time Noise-Shaping SAR ADC With Duty-Cycled Gm-C Integrator

This article presents a first-order continuous-time (CT) noise-shaping successive-approximation-register (NS-SAR) analog-to-digital converter (ADC). Different from other NS-SAR ADCs in literature, which are discrete-time (DT), this ADC utilizes a CT Gm-C integrator to realize an inherent anti-aliasing function. To cope with the timing conflict between the DT SAR ADC and the CT integrator, the sampling switch of the SAR ADC is removed, and the integrator is duty cycled to leave 5% of the sampling clock period for the SAR conversion. Redundancy is added to track the varying ADC input due to the absence of the sampling switch. A theoretical analysis shows that the 5% duty-cycling has negligible effects on the signal transfer function (STF) and the noise transfer function. The output swing and linearity requirements for the integrator are also relaxed thanks to the inherent feedforward path in the NS-SAR ADC architecture. Fabricated in 65-nm CMOS, the prototype achieves 77.3-dB peak signal-to-noise and distortion ratio (SNDR) in a 62.5-kHz bandwidth while consuming <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$13.5~\mu \text{W}$ </tex-math></inline-formula> , leading to a Schreier figure of merit (FoM) of 174.0 dB. Moreover, it provides 15-dB attenuation in the alias band.

A Review of Noise Reduction Techniques in Noise-shaping SAR ADCs

Noise-shaping successive-approximation-register (NS-SAR) ADCs have become one of the most promising candidates for high-resolution data converters over the past decade. This is due to the fact that they combine the advantages of delta-sigma modulation and SAR ADCs. In this hybrid architecture, the quantizer and residue feedback DAC can be replaced by SAR, a replacement which achieves high SNR while also benefiting from superior power efficiency and low cost. For NS-SAR ADCs, various implementations of loop filters for residue processing exist that can realize the noise transfer function (NTF) for NS effects. In addition, many noise reduction techniques have been proposed that suppress additional noises not shaped by NTF. This paper describes the basics of NS-SAR ADCs while also reviewing noise reduction techniques, which include the implementation of a loop filter for residue handling, kT/C noise rejection, and capacitive DAC mismatch error shaping. It also outlines advanced architectures that can overcome the limitations of NS-SAR ADCs.

An 84-dB-SNDR Low-OSR Fourth-Order Noise-Shaping SAR With an FIA-Assisted EF-CRFF Structure and Noise-Mitigated Push-Pull Buffer-in-Loop Technique

To design a low-oversampled high-resolution noise-shaping successive approximation register (NS-SAR) analog-to-digital converters (ADCs), two main bottlenecks need to be addressed. One is to implement high-order optimized NS with simple and low-power hardware that maximally preserves a SAR’s efficient nature, and the other is to alleviate the sampling noise and input driving burden. This article presents a fourth-order NS-SAR ADC that synergistically addresses both challenges. It proposes an innovative error feedback-cascaded resonator feed-forward (EF-CRFF) structure and a noise-mitigated buffer-in-loop (BIL) technique. The former balances the robustness and energy efficiency by combining the merits of EF and CRFF structures, while the latter ensures the ADC to be low noise and easy-to-drive simultaneously. Prototyped in 65-nm CMOS technology, this work achieves 84.1-dB signal-to-noise-distortion ratio (SNDR) with 500-kHz bandwidth (BW) under a small OSR of 5. The prototype consumes 133.8- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> power under 1.2-V supply (including the power of in-loop buffer under 2-V supply), leading to a 180-dB Schreier figure of merit (FoM).

A fully dynamic third-order EF-CIFF noise-shaping SAR ADC with NTF zeros optimization and passive integration

In this paper, a third-order noise-shaping successive approximation register (NS-SAR) analog-to-digital converter (ADC) is proposed which is simple and fully dynamic. A passive integrator is utilized in the feed-forward (FF) path of a second-order NS-SAR ADC with 2nd-order error-feedback (EF) filter to reduce the effect of inband quantization and comparator noise. The integrator implements a passive gain of 4x to make up its loss arising from the charge sharing between the integrator and digital-to-analog converter capacitors at the integration phase. Another advantage of the proposed structure is employing a simple low noise and low power one-input pair comparator unlike many published NS-SAR ADCs which use a comparator with multi-input pairs leading to enhanced comparator input-referred noise and power consumption. In this work, the zeros of the noise transfer function are optimized to enhance inband noise suppression. The proposed ADC is designed at circuit level using 0.18 μm TSMC CMOS technology with Cadence Virtuoso tool. The oversampling ratio, sampling frequency, and bandwidth are 8, 2.5 MS/s, and 156.25 kHz, respectively. According to the detailed post-layout simulation results, the achieved signal-to-noise and distortion ratio of the simulated ADC is 83.1 dB with 70.3 µW power consumption from a 1.1 V supply.

An 80 dB Second-order Noise Shaping SAR ADC using Differential Integral Capacitors and Comparator with Voltage Gain Calibration

A second-order noise shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) is proposed for sensor interface applications. It consists of a capacitor-resistor hybrid digital-to-analog-converter (C-R DAC) with 10-bit resolution, a comparator with three inputs, a SAR logic, and a second passive integrator using two differential capacitors. The use of a C-R DAC and two differential capacitors reduces the capacitor area of the conventional NS SAR ADC by 86.25%. Voltage gain calibration for the three-input comparator is proposed to maximize the performance of the NS SAR ADC. The proposed second-order NS ADC is designed using a 180-nm CMOS process with a supply of 1.8 V. The proposed second-order NS SAR ADC with an over sampling ratio of 8 has a SNDR of 80.18 dB and an ENOB of 13.03 bits. Its area and power consumption are 0.165 ㎟ and 248 μW, respectively.

A Unity‐Gain Buffer Assisted Noise‐Shaping SAR ADC Based on Error‐Feedback Structure

The passive noise-shaping successive approximation register (NS-SAR) analog-to-digital converter (ADC) demonstrates high performance in resolution improvement, power reduction, and process scaling, while its charge-sharing loss and limited bandwidth weaken the noise-shaping effect. This paper presents a first-order NS-SAR ADC based on error-feedback (EF) structure to realize high-efficiency noise shaping. It employs a lossless EF path by using a set of ping-pong switching capacitors with passive signal-residue summation technique. The proposed first-order EF NS-SAR prototype can be promoted to multi-order structure with the minor modification. Verified by simulation in 65-nm CMOS process, the proposed 9-bit NS-SAR ADC consumes 183.66 μW when operating at 20 MS/s with the supply voltage of 1.2 V. At the oversampling ratio of 16, it achieves a peak signal-to-noise-and-distortion ratio of 81 dB, yielding Schreier figure of merit of 176.32 dB.

A passive second‐order noise‐shaping SAR ADC architecture with increased freedom in NTF synthesis and relaxed clock‐jitter issue

Noise-shaping (NS) successive approximation register (SAR) analogue-to-digital converters (ADCs) are an attractive architecture for power and area efficiency in moderate resolution and bandwidth applications. NS SAR ADCs employing a passive integrator are good candidates for their omission of power-hungry and scaling-unfriendly amplifiers. However, existing passive NS SAR ADCs have a very limited degree of freedom in realising their noise transfer function (NTF), resulting in poor in-band noise suppression. In this letter, a passive switched-capacitor 2nd-order NS SAR ADC that is the first of its kind to offer controllable complex poles to optimise the NTF is proposed. This is achieved by eliminating a capacitor charge clearing operation in a conventional 1st-order NS SAR. The proposed NS SAR ADC also offers simple circuits insensitive to process–voltage–temperature (PVT) variations, and small area with only two extra clock phases. Transistor-level circuit simulation of a 7-bit, 8-MHz bandwidth, 128 MS/s prototype in a 65-nm CMOS shows a 70 dB signal to noise and distortion ratio (SNDR), an improvement of 19 dB compared to that of a regular 7-bit SAR ADC.

OTA-Free 1–1 MASH ADC Using Fully Passive Noise-Shaping SAR &amp; VCO ADC

We present an OTA-free 1–1 multi-stage noise-shaping (MASH) analog-to-digital converter (ADC) utilizing a fully passive noise-shaping successive approximation register (NS-SAR) as the first stage and an open-loop ring voltage-controlled oscillator (VCO) as the second stage. The key contribution of this work is to address the challenge of driving large sampling capacitors for high-resolution NS-SAR. The proposed architecture allows a low-resolution NS-SAR stage and leverages residue attenuation due to passive charge sharing in the NS-SAR to linearize the VCO. The MASH architecture suppresses quantization noise and SAR comparator noise at the ADC output, and the high pass shapes VCO thermal noise. In addition, we demonstrate a computationally inexpensive foreground inter-stage gain calibration algorithm for the proposed ADC architecture. The prototype ADC consumes 0.16 mW while achieving an SNDR/DR of 71.5/75.8 dB over a 1.1-MHz bandwidth and Walden FoM of 23.3 fJ/step, which is the lowest in 65-nm technology.

A 625kHz-BW, 79.3dB-SNDR Second-Order Noise-Shaping SAR ADC Using High-Efficiency Error-Feedback Structure

This brief presents a compact and energy efficient noise-shaping successive-approximation-register (NS-SAR) analog-to-digital converter (ADC) based on the error-feedback (EF) structure. Different from most prior works adopting the cascaded integrator feed-forward (CIFF) structure, the proposed architecture employs unity-gain buffer and delay elements operated in a ping-pong manner to perform EF function. Since to the lossless residue extraction and summation, it exhibits high efficiency in realizing the strong noise-shaping (NS) effect. Fabricated in a 65-nm 1P9M CMOS technology, the prototype NS-SAR ADC consumes <inline-formula> <tex-math notation="LaTeX">$113.02~\mu \text{W}$ </tex-math></inline-formula> when operating at a 1.2-V supply voltage and at a sampling rate of 20 MS/s. It achieves a peak Schreier FoM of 176.73 dB with a signal to noise and distortion-ratio (SNDR) of 79.3 dB at an oversampling ratio (OSR) of 16.

Low-Power SAR ADCs: Basic Techniques and Trends

With the advent of small, battery-powered devices, power efficiency has become of paramount importance. For Analog-to-Digital-Converters (ADCs), the Successive Approximation Register (SAR) architecture plays a prominent role thanks to its ability to combine power efficiency with a simple architecture, a broad application scope, and technology portability. In this review article, the basic design challenges for low-power SAR ADCs are summarized and several design techniques are illustrated. Further, the limitations of SAR ADCs are outlined and hybrid architecture trends, like noise-shaping SAR ADCs and pipelined SAR ADCs, are briefly introduced and clarified with examples.

A Capacitor-Reused 2b/Cycle Active-Passive Second-order Noise-Shaping SAR ADC

In this manuscript, a novel 2nd-order noise-shaping successive-approximation register (NS-SAR) analog-to-digital converter (ADC) is introduced for potential application in wideband continuous-time (CT) ΔΣ modulators. The proposed NS-SAR employs a special active-passive residue filter that reuses the capacitor of the reference digital-to-analogue converter (DAC) of the SAR. Compared to the conventional NS-SAR that uses an active residue filter, the proposed approach saves one power-hungry amplifier and four replica DACs. An asynchronous 2b/cycle conversion scheme is adopted for a reduced excessive loop delay (ELD) in the modulator. Transistor-level simulations in a 65nm CMOS process are presented to demonstrate the principle of the proposed NS-SAR.

A 13.8-ENOB Fully Dynamic Third-Order Noise-Shaping SAR ADC in a Single-Amplifier EF-CIFF Structure With Hardware-Reusing kT/C Noise Cancellation

To design noise-shaping successive approximation register (NS-SAR) analog-to-digital converters (ADCs) with high resolution and good power efficiency, two key bottlenecks need to be addressed. One is to realize a high-order loop filter with low circuit overhead, and the other is to mitigate the thermal noise. This article presents an NS-SAR ADC that synergistically addresses both challenges. To achieve high-order efficiency, it proposes an innovative error feedback-cascaded integrator feedforward (EF-CIFF) structure that realizes third-order noise shaping using only a single amplifier. It combines the merits of both structures, showing improved robustness, and is free of dc offset concern. On reducing the kT/C noise, this work features a sampling kT/C noise cancellation (SNC) technique that reuses the native hardware of the EF-CIFF structure. An open-loop self-quenching floating-inverter dynamic amplifier (FIDA) is used to support all amplification with low noise and power. Prototyped in 65-nm CMOS, this work achieves 84.8-dB signal-to-noise-distortion ratio (SNDR) with 625-kHz bandwidth (BW) (OSR = 8) and 119 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> , leading to 182-dB Schreier Figure of Merit (FoM). It uses only 0.8-pF input capacitance, which is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5\times $ </tex-math></inline-formula> smaller than prior NS-SAR ADCs with similar oversampling ratio (OSR) and SNDR.

An 85 dB DR 4 MHz BW Pipelined Noise-Shaping SAR ADC With 1–2 MASH Structure

A pipelined noise-shaping successive approximation register (NS-SAR) ADC with 1–2 multistage noise-shaping (MASH) structure is presented. Two-stage pipelined structure consisting of 5 bit NS-SAR and 4 bit NS-SAR quantizers enables 3rd-order noise-shaping. A single operational transconductance amplifier (OTA) is shared by an integrator for noise-shaping and a residue amplifier for pipelining to maximize the power efficiency. The measured dynamic range (DR) is 84.6 dB when the sampling rate is 83.3 MS/s, bandwidth is 4 MHz, and power consumption is 3.5 mW showing Schreier figure-of-merit (FoM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S,DR</sub> ) of 175.2 dB. The proposed ADC structure greatly relaxes design requirement of each SAR quantizer and can achieve high resolution and wide bandwidth with good power efficiency.

A 90-dB-SNDR Calibration-Free Fully Passive Noise-Shaping SAR ADC With 4× Passive Gain and Second-Order DAC Mismatch Error Shaping

Noise-shaping (NS) successive approximation register (SAR) analog-to-digital converters (ADCs) using passive loop filters have drawn the increasing attentions owing to their simplicity, low power, zero static current, and PVT robustness. However, prior works show the limited resolution because of two main challenges: the thermal noise and the digital-to-analog converter (DAC) mismatch. This article presents a high-resolution full passive NS SAR ADC. It uses an efficient NS filter architecture that realizes a 4 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> passive gain and the passive summation, significantly reducing the total thermal noise. It also realizes the second-order DAC mismatch error shaping (MES) that is tone-free. A digital prediction is proposed to solve the signal-range loss issue caused by the MES, recovering the ADC input signal range to the full swing. A prototype NS SAR ADC is implemented in 40-nm CMOS process. It measures 90.5-dB signal-to-noise-and-distortion ratio (SNDR) and 94.3-dB dynamic range (DR) over 40-kHz bandwidth without any calibration. It consumes 67.4 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> power from a 1.1-V supply and occupies 0.061 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area.

Time-interleaved Noise-shaping SAR ADC based on CIFF Architecture with Redundancy Error Correction Technique

A time-interleaved noise-shaping (TINS) successive approximation register (SAR) analog-to-digital converter (ADC) based on the cascade of integrators with feed-forward (CIFF) architecture can achieve a high resolution and wide bandwidth with a high energy efficiency. Because it does not use the summation pre-amplifier, the energy efficiency obtained using the proposed ADC is higher than that of the TINS-SAR ADC based on the error-feedback (EF) architecture. In addition, the proposed ADC uses only one final residue sampling capacitor, and thus, the complexity of the circuit is reduced. The proposed ADC is implemented in a 65-nm CMOS process. According to the post-layout simulation result, a signal to noise and distortion ratio (SNDR) of 69.2 dB can be obtained for a sampling rate of 800 MS/s and bandwidth of 100 MHz with a high energy efficiency.

A 12.1bit-ENOB noise shaping SAR ADC for biosensor applications

This paper proposes a low power fully-passive noise shaping successive approximation register analog-to-digital converter (SAR ADC) for biosensor applications. The proposed ADC includes a second-order fully-passive integrator achieves a second-order noise transfer function. With an independent residue voltage generator to adjust common voltage between the main and residue path, the power efficiency of three differential inputs comparator is improved. The 0.18μm CMOS prototype chip occupies a total area of 1.37 mm2 with a core area of 0.58 mm2 and consumes 131 μW from a 1.3 V supply. The proposed SAR ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 74.8 dB and a peak spurious-free dynamic range (SFDR) of 89.7 dB at a sampling rate of 8 MSPS and oversampling rate of 16, leading to the Schreier figure of merit (FoMs) of the proposed ADC of 167.4 dB.

Conception and Simulation of a 2-Then-1-Bit/Cycle Noise-Shaping SAR ADC

A 2-then-1-bit/cycle noise-shaping successive-approximation register (SAR) analog-to-digital converter (ADC) for high sampling rate and high resolution is presented. The conversion consists of two phases of a coarse 2-bit/cycle SAR conversion for high speed and a fine 1-bit/cycle noise-shaping SAR conversion for high accuracy. The coarse conversion is performed by both voltage and time comparison for low power consumption. A redundancy after the coarse conversion corrects the error caused by a jitter noise during the time comparison. Additionally, a mismatch error between signal and reference paths is eliminated with the help of a tail-current-sharing comparator. The proposed ADC was designed in a 28 nm CMOS process, and the simulation result shows a 68.2 dB signal-to-noise distortion (SNDR) for a sampling rate of 480 MS/s and a bandwidth of 60 MHz with good energy efficiency.