Abstract
The passive noise-shaping successive approximation register (NS-SAR) analog-to-digital converter (ADC) demonstrates high performance in resolution improvement, power reduction, and process scaling, while its charge-sharing loss and limited bandwidth weaken the noise-shaping effect. This paper presents a first-order NS-SAR ADC based on error-feedback (EF) structure to realize high-efficiency noise shaping. It employs a lossless EF path by using a set of ping-pong switching capacitors with passive signal-residue summation technique. The proposed first-order EF NS-SAR prototype can be promoted to multi-order structure with the minor modification. Verified by simulation in 65-nm CMOS process, the proposed 9-bit NS-SAR ADC consumes 183.66 μW when operating at 20 MS/s with the supply voltage of 1.2 V. At the oversampling ratio of 16, it achieves a peak signal-to-noise-and-distortion ratio of 81 dB, yielding Schreier figure of merit of 176.32 dB.
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