Abstract
This paper presents a second-order noise-shaping successive approximation register (NS-SAR) analog-to-digital converter (ADC) employing the error-feedback (EF) structure. With the finite impulse response (FIR) filter based on a single operational transconductance amplifier (OTA), it realizes noise transfer function (NTF) zeros optimization. The specifications of OTA are relaxed without high-gain and fast-settling. To mitigate the harmonic distortion caused by capacitor mismatch, thermometer-coded 4-bit MSBs are implemented with the data weighted averaging (DWA) technique. The overall architecture is simple and robust. It does not need additional complicated digital calibrations, and only requires minor modifications to the standard SAR ADC. Design and simulation in a 130 nm CMOS process, the prototype consumes 96 μW of power when operating at 1 MS/s sampling frequency. The proposed ADC achieves peak Schreier FoM of 165 dB with 76.95 dB signal to noise and distortion ratio (SNDR) and 97.34 dB spurious free dynamic range (SFDR) at an oversampling ratio (OSR) of 8.
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