A passive second‐order noise‐shaping SAR ADC architecture with increased freedom in NTF synthesis and relaxed clock‐jitter issue

Abstract

Noise-shaping (NS) successive approximation register (SAR) analogue-to-digital converters (ADCs) are an attractive architecture for power and area efficiency in moderate resolution and bandwidth applications. NS SAR ADCs employing a passive integrator are good candidates for their omission of power-hungry and scaling-unfriendly amplifiers. However, existing passive NS SAR ADCs have a very limited degree of freedom in realising their noise transfer function (NTF), resulting in poor in-band noise suppression. In this letter, a passive switched-capacitor 2nd-order NS SAR ADC that is the first of its kind to offer controllable complex poles to optimise the NTF is proposed. This is achieved by eliminating a capacitor charge clearing operation in a conventional 1st-order NS SAR. The proposed NS SAR ADC also offers simple circuits insensitive to process–voltage–temperature (PVT) variations, and small area with only two extra clock phases. Transistor-level circuit simulation of a 7-bit, 8-MHz bandwidth, 128 MS/s prototype in a 65-nm CMOS shows a 70 dB signal to noise and distortion ratio (SNDR), an improvement of 19 dB compared to that of a regular 7-bit SAR ADC.