Noise-shaping Successive Approximation Register Research Articles

A 12.1bit-ENOB noise shaping SAR ADC for biosensor applications

This paper proposes a low power fully-passive noise shaping successive approximation register analog-to-digital converter (SAR ADC) for biosensor applications. The proposed ADC includes a second-order fully-passive integrator achieves a second-order noise transfer function. With an independent residue voltage generator to adjust common voltage between the main and residue path, the power efficiency of three differential inputs comparator is improved. The 0.18μm CMOS prototype chip occupies a total area of 1.37 mm2 with a core area of 0.58 mm2 and consumes 131 μW from a 1.3 V supply. The proposed SAR ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 74.8 dB and a peak spurious-free dynamic range (SFDR) of 89.7 dB at a sampling rate of 8 MSPS and oversampling rate of 16, leading to the Schreier figure of merit (FoMs) of the proposed ADC of 167.4 dB.

Conception and Simulation of a 2-Then-1-Bit/Cycle Noise-Shaping SAR ADC

A 2-then-1-bit/cycle noise-shaping successive-approximation register (SAR) analog-to-digital converter (ADC) for high sampling rate and high resolution is presented. The conversion consists of two phases of a coarse 2-bit/cycle SAR conversion for high speed and a fine 1-bit/cycle noise-shaping SAR conversion for high accuracy. The coarse conversion is performed by both voltage and time comparison for low power consumption. A redundancy after the coarse conversion corrects the error caused by a jitter noise during the time comparison. Additionally, a mismatch error between signal and reference paths is eliminated with the help of a tail-current-sharing comparator. The proposed ADC was designed in a 28 nm CMOS process, and the simulation result shows a 68.2 dB signal-to-noise distortion (SNDR) for a sampling rate of 480 MS/s and a bandwidth of 60 MHz with good energy efficiency.

A Fully Dynamic Low-Power Wideband Time-Interleaved Noise-Shaping SAR ADC

This article proposes a fully dynamic, low-power, wideband, time-interleaved (TI), noise-shaping (NS) successive-approximation-register (SAR) analog-to-digital converter (ADC) based on the cascade of integrators with feedforward (CIFF) architecture. Both the interleaving operation and the loop filter are implemented by using the fully passive switched-capacitor circuits. The feedforward summation is realized by a multi-path dynamic comparator. The overall noise transfer function (NTF) is highly robust against process, voltage, and temperature (PVT) variations since the NTF is determined by device ratios. This allows the NTF zeros to be close to 1, with a good NS effect. Compared with a recently published TI NS SAR based on the error-feedback (EF) architecture, this work does not need a static amplifier, thus leading to the fully dynamic operation. Meanwhile, it eliminates the dependence of NTF on the PVT-sensitive amplifier gain. Implemented in a 40-nm CMOS process, the prototype ADC achieves an SNDR of 69.1 dB, a bandwidth of 50 MHz, and a power consumption of 8.5 mW under a 1.1-V supply, leading to a Walden FoM of 36.3 fJ/conv.-step.

A 74-dB Dynamic-Range 625-kHz Bandwidth Second-Order Noise-Shaping SAR ADC Utilizing a Temperature-Compensated Dynamic Amplifier and a Digital Mismatch Calibration

This paper presents the design of a 2nd-order Noise-Shaping (NS) Successive-Approximation-Register (SAR) Analog-to-Digital Converter (ADC) employing a cascade of temperature-compensated dynamic amplifier and a ring amplifier in the feedback path to realize a low-power/low-noise loop filter that is robust to temperature variation. A new mismatch calibration technique optimized for a noise-shaping SAR ADC is also presented to overcome the challenge of finding correct digital bit weights for NS SAR ADCs. Fabricated in 65 nm Complementary Metal-Oxide-Semiconductor (CMOS) process, the prototype ADC demonstrates a peak Signal-to-Noise-and-Distortion Ratio (SNDR) of 71.35 dB and a dynamic range of 74 dB with a signal bandwidth of 625 kHz. Over 80-degree of the temperature range, the ADC exhibits only 2 dB drop in SNDR thanks to the temperature-compensated dynamic amplifier. With a total power consumption of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$130~\mu \text{W}$ </tex-math></inline-formula> , the ADC achieves Walden Figure-of-Merit (FoM) of FoM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text {W}}= 34.4$ </tex-math></inline-formula> fJ and Schreier FoM of FoM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text {S,DR}}=171$ </tex-math></inline-formula> dB, respectively.

A Second-Order Noise-Shaping SAR ADC Using Two Passive Integrators Separated by the Comparator

This brief presents a second-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with two passive integrators. Due to the separation of the preamplifier, these two integrators become independent of each other and the size of the second integrator can be reduced. The NS SAR also realizes the zeros optimization of the noise transfer function (NTF). The analysis shows the NS performance of the proposed ADC is insensitive to the gain variation of the multipath comparator. To mitigate the harmonic distortion caused by capacitor mismatch, thermometer-code 4-bit MSBs are implemented with data weighted averaging (DWA) technique. The overall architecture is simple and robust, which only requires minor modifications to the standard SAR ADC. A prototype 9-bit NS-SAR ADC is designed and simulated in a 130-nm CMOS process. It consumes $59.9~\mu \text{W}$ of power when operating at 2-MS/s sampling frequency. The proposed ADC achieves peak Schreier figure of merits (FoMs) of 171.9 dB with 78.69-dB signal-to-noise-and-distortion ratio (SNDR) at an oversampling ratio (OSR) of 8.

Error suppression techniques for energy-efficient high-resolution SAR ADCs

The successive approximation register (SAR) is one of the most energy-efficient analog-to-digital converter (ADC) architecture for medium-resolution applications. However, its high energy efficiency quickly diminishes when the target resolution increases. This is because a SAR ADC suffers from several major error source, including the sampling kT/C noise, the comparator noise, and the DAC mismatch. These errors are increasing hard to address in high-resolution SAR ADCs. This paper reviews recent advances on error suppression techniques for SAR ADCs, including the sampling kT/C noise reduction, the noise-shaping (NS) SAR, and the mismatch error shaping (MES). These techniques aim to boost the resolution of SAR ADCs while maintaining their superior energy efficiency.

A second-order noise-shaping SAR ADC with error-feedback structure and data weighted averaging

This paper presents a second-order noise-shaping successive approximation register (NS-SAR) analog-to-digital converter (ADC) employing the error-feedback (EF) structure. With the finite impulse response (FIR) filter based on a single operational transconductance amplifier (OTA), it realizes noise transfer function (NTF) zeros optimization. The specifications of OTA are relaxed without high-gain and fast-settling. To mitigate the harmonic distortion caused by capacitor mismatch, thermometer-coded 4-bit MSBs are implemented with the data weighted averaging (DWA) technique. The overall architecture is simple and robust. It does not need additional complicated digital calibrations, and only requires minor modifications to the standard SAR ADC. Design and simulation in a 130 ​nm CMOS process, the prototype consumes 96 ​μW of power when operating at 1 ​MS/s sampling frequency. The proposed ADC achieves peak Schreier FoM of 165 ​dB with 76.95 ​dB signal to noise and distortion ratio (SNDR) and 97.34 ​dB spurious free dynamic range (SFDR) at an oversampling ratio (OSR) of 8.

A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier

This article presents a second-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with a process, voltage, and temperature (PVT)-robust closed-loop dynamic amplifier. The proposed closed-loop dynamic amplifier combines the merits of closed-loop architecture and dynamic operation, realizing robustness, high accuracy, and high energy-efficiency simultaneously. It is embedded in the loop filter of an NS SAR design, enabling the first fully dynamic NS-SAR ADC that realizes sharp noise transfer function (NTF) while not requiring any gain calibration. Fabricated in 40-nm CMOS technology, the prototype ADC achieves an SNDR of 83.8 dB over a bandwidth of 625 kHz while consuming only $107~\mu \text{W}$ . It results in an SNDR-based Schreier figure-of-merit (FoM) of 181.5 dB.

An opamp-free second-order noise-shaping SAR ADC with 4$$\times$$ passive gain using capacitive charge pump

This paper presents a compact and robust opamp-free noise shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC). The proposed NS SAR ADC adopts extra one passive feed-forward path summing in realizing second-order noise shaping with the minimum modification to a standard SAR. Compared with previous works, the noise sources of residue sampling and first-order integration on filter capacitors are obviated. It implements 4 $$\times$$ passive gain by capacitive charge-pump techniques that compensates the partial loss of residue voltage and relaxes the specifications of comparator. According to the behavioral modeling and simulation results, an ENOB of 16.88-bit is achieved based on a 10-bit DAC array, at the OSR of 16. Through utilizing the Monte Carlo simulation, the proposed ADC architecture is proven to be a robust system.

2nd-Order shaping technique of the DAC mismatch error in noise shaping SAR ADCs

A switching scheme to realize 2nd-order digital-to-analog converter (DAC) mismatch error shaping (MES) technique in the high-resolution noise shaping successive approximation register analogue-to-digital converters (NS SAR ADCs) is proposed. By feeding back the combination of the least significant bit (LSB) DAC mismatch errors in two previous cycles, the DAC mismatch error is 2nd-order shaped. The scheme only requires an extra reference voltage and triples LSB DAC, which leads to simple control logic. According to the simulation, the spurious-free dynamic range is improved 10 dB more than the 1st-order MES.

A 12.5-MHz Bandwidth 77-dB SNDR SAR-Assisted Noise Shaping Pipeline ADC

This article presents a successive approximation register (SAR)-assisted noise-shaping (NS) pipeline architecture which breaks the speed bottleneck of the existing SAR or SAR-assisted-type NS analog-to-digital converters (ADCs). Rather than only for residue amplification and pipeline operation, the multiplying digital-to-analog converter (MDAC) is also reused as unity buffer and analog adder to realize the NS with error feedback (EF) structure in this design. While incorporating the proposed alternative loading capacitor (ALC) technique, an ideal first-order noise transfer function (NTF) is realized without additional feedback phase and only with a small analog circuit overhead. Unlike other NS SAR ADCs that involved amplification, the inter-stage gain attenuates the noise from the second-stage comparator, thus leading to both high speed and resolution. Fabricated in a 65-nm CMOS process, the prototype achieves a signal-to-noise-and-distortion ratio (SNDR) of 77.1 dB over 12.5-MHz bandwidth (BW) with only over-sampling ratio (OSR) of 8. Under a 1.2-V supply voltage, the ADC consumes 4.5 mW and exhibits a Scherier figure of merit (FoM) of 171.5 dB.

Dither‐based background calibration of capacitor mismatch and gain error in pipelined noise shaping successive approximation register ADCs

A dither-based background calibration with data-weighted averaging logic to correct capacitor mismatch and inter-stage gain error in pipelined noise shaping successive approximation register ADCs is proposed. By injecting the dither signal in the background, the inter-stage gain is obtained. Besides, the data-weighted averaging logic is adopted to dissipate harmonics caused by the mismatch of capacitors. Owing to the effective combination of the two methods, there is no need to detect the conditions of injecting the dither signal. As a result, the calibration requires simple logic and adds little analogue overhead.

8.4‐to‐16‐bit resolution, 1‐to‐16 kHz bandwidth ADC with programmable‐gain functionality for multi‐sensor applications

A resolution-reconfigurable, bandwidth-scalable analogue-to-digital converter (ADC) with programmable-gain (PG) functionality for a multi-sensor system, which encompasses various signals such as bio-signals and battery-level, is presented. In PG and low-power mode, a PG first-order noise-shaping (NS) successive-approximation register (SAR) ADC achieves 8.4-to-10.2-bit operating up to 16 kHz while providing a gain of 1/2/4. The PG NS SAR ADC can be reconfigured as an adder and a quantiser in a delta-sigma (ΔΣ) modulator enhancing the order of the modulator for high-resolution. The third-order ΔΣ modulator achieves 16.1 bits in a bandwidth of 1 kHz. The work is implemented in a 0.18 μm CMOS process with a 1.8 V power supply.

A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure

The noise-shaping successive approximation register (NS-SAR) analog-to-digital converter (ADC) is an emerging hybrid architecture that achieves high resolution and power efficiency simultaneously by combining the merits of the SAR ADC and the $\Delta \Sigma $ ADC. Most prior works adopting the cascaded integrator feed-forward (CIFF) structure demonstrate inefficiency in realizing optimized noise transfer function (NTF). This paper presents a second-order NS-SAR ADC employing the error-feedback (EF) structure to realize complex NTF zeros for noise-shaping enhancement with the minimum modification to a standard SAR. It implements a low-power scaling-friendly EF path by using a passive finite impulse response (FIR) and a comparator-reused dynamic amplifier with process-voltage-temperature (PVT) tracking background calibration. Fabricated in 40-nm CMOS, the prototype chip consumes $84~\mu \text{W}$ when operating at 10 MS/s. The NS-SAR achieves peak Schreier FoM of 178 dB with 79-dB signal to noise and distortion ratio (SNDR) at an oversampling ratio (OSR) of 8.

160 MS/s 20 MHz bandwidth third‐order noise shaping SAR ADC

This Letter proposes an operational-amplifier free with an embedded passive gain technique to implement an oversampling, noise shaping successive approximation register (SAR) ADCs. In the proposed scheme, the comparator noise, quantisation noise, settling errors and DAC thermal noise are alleviated. A third-order noise shaping SAR ADC with inserted passive gain design in 40 nm CMOS technology is well suited for low power application because of using passive elements like capacitors and switches. Due to the oversampling and shaping scheme, the structure can be used for high-speed and high-resolution operation.

Passive Noise Shaping in SAR ADC With Improved Efficiency

This brief reports a passive noise-shaping (PNS) scheme for successive approximation register (SAR) analog-to-digital converter (ADC) based on the two-step integration with passive gain and comparator gain techniques. The analysis shows that the proposed method achieves a better noise-shaping (NS) efficiency than prior arts, which enhances the noise attenuation by 14 dB. A design example is provided which further adopts the delta-sampling technique to relieve the conversion efficiency loss due to the oversampling in the NS SAR ADC. The efficiency of the proposed PNS scheme and the performance of the ADC are verified by simulation achieving a 13.2 effective number of bits with a 10-b ADC architecture and eight conversion cycles for a signal bandwidth of 2 MHz sampled at 100 MS/s. The calculated Schreier figure of merit (FoM) and Walden FoM are 176.8 dB and 16 fJ/conv.-step, respectively.

A simple structure for noise-shaping SAR ADC in 90 nm CMOS technology

This paper presents a simple structure for error feedback based noise-shaping successive approximation register (NSSAR) analog-to-digital converter (ADC), which obviates the need for a high output swing, fast-settling and high gain Operational Transconductance Amplifier (OTA). The ADC has a simple structure and its quantization noise is extracted and transferred via a finite impulse response (FIR) filter, without any attenuation. To make a good matching, a 5-bit segmented array is utilized as a digital-to-analog converter (DAC). In this way, the required total capacitance of the ADC is reduced more than 96% compared to a 10-bit conventional SAR (CSAR) ADC. Also, due to noise-shaping property the comparator specifications are relaxed. The ADC is designed and simulated in 90nm CMOS technology with HSPICE simulator. Simulation results show that the ADC's average power consumption is about 4.4μW at a 0.5V power supply. By using an oversampling ratio (OSR) of 16, the ADC achieved maximum SNDR and SFDR of 59.6dB and 58dB, respectively, from transient noise simulation. The figure of merit (FoM) is about 56.4fJ/conversion-step.