Abstract
This paper presents the design of a 2nd-order Noise-Shaping (NS) Successive-Approximation-Register (SAR) Analog-to-Digital Converter (ADC) employing a cascade of temperature-compensated dynamic amplifier and a ring amplifier in the feedback path to realize a low-power/low-noise loop filter that is robust to temperature variation. A new mismatch calibration technique optimized for a noise-shaping SAR ADC is also presented to overcome the challenge of finding correct digital bit weights for NS SAR ADCs. Fabricated in 65 nm Complementary Metal-Oxide-Semiconductor (CMOS) process, the prototype ADC demonstrates a peak Signal-to-Noise-and-Distortion Ratio (SNDR) of 71.35 dB and a dynamic range of 74 dB with a signal bandwidth of 625 kHz. Over 80-degree of the temperature range, the ADC exhibits only 2 dB drop in SNDR thanks to the temperature-compensated dynamic amplifier. With a total power consumption of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$130~\mu \text{W}$ </tex-math></inline-formula> , the ADC achieves Walden Figure-of-Merit (FoM) of FoM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text {W}}= 34.4$ </tex-math></inline-formula> fJ and Schreier FoM of FoM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text {S,DR}}=171$ </tex-math></inline-formula> dB, respectively.
Highlights
The noise-shaping successive-approximation-register (NSSAR) analog-to-digital converter (ADC) [1] is an emerging oversampled ADC architecture that has been gaining increasing popularity for high resolution data converter designs
While the traditional LS minimization is still applicable to the NS-SAR ADC calibration, using the same method in NSSAR ADCs leads to sub-optimal bit weights
This paper presented a 2nd-order noise-shaping SAR ADC design in 65-nm Complementary Metal-Oxide-Semiconductor (CMOS) with peak Signal-to-Noise-and-Distortion Ratio (SNDR) of 71.35 dB over 625 kHz bandwidth
Summary
The noise-shaping successive-approximation-register (NSSAR) analog-to-digital converter (ADC) [1] is an emerging oversampled ADC architecture that has been gaining increasing popularity for high resolution data converter designs. An opamp-based switched-capacitor circuit has been widely used to realize such a discrete-time analog signal processing block, but using a high-gain opamp drawing constant current in a loop filter leads to power-hungry ADC designs [1]. To overcome this issue, several new ideas have been introduced. Using the algorithm developed for Nyquist ADCs may be sub-optimal when applied to finding optimal bit weights for noise-shaped ADCs. As an expanded work of the article presented in [14], this paper presents two new approaches that can advance the design of NS-SAR ADCs. First, we report a low-power loop filter topology utilizing a cascade of a temperaturecompensated dynamic amplifier and a ring amplifier. Such a gain requirement can still be a design bottleneck when one wants to use a low-power dynamic amplifier for EF NS-SAR because achieving gain beyond 4 ∼ 6 [V/V] is not achievable [6], [16] unless sophisticated techniques such as using a constant commonmode current [2] or a positive feedback [3] are used
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