A simple structure for noise-shaping SAR ADC in 90 nm CMOS technology

Abstract

This paper presents a simple structure for error feedback based noise-shaping successive approximation register (NSSAR) analog-to-digital converter (ADC), which obviates the need for a high output swing, fast-settling and high gain Operational Transconductance Amplifier (OTA). The ADC has a simple structure and its quantization noise is extracted and transferred via a finite impulse response (FIR) filter, without any attenuation. To make a good matching, a 5-bit segmented array is utilized as a digital-to-analog converter (DAC). In this way, the required total capacitance of the ADC is reduced more than 96% compared to a 10-bit conventional SAR (CSAR) ADC. Also, due to noise-shaping property the comparator specifications are relaxed. The ADC is designed and simulated in 90nm CMOS technology with HSPICE simulator. Simulation results show that the ADC's average power consumption is about 4.4μW at a 0.5V power supply. By using an oversampling ratio (OSR) of 16, the ADC achieved maximum SNDR and SFDR of 59.6dB and 58dB, respectively, from transient noise simulation. The figure of merit (FoM) is about 56.4fJ/conversion-step.