Abstract
A 2-then-1-bit/cycle noise-shaping successive-approximation register (SAR) analog-to-digital converter (ADC) for high sampling rate and high resolution is presented. The conversion consists of two phases of a coarse 2-bit/cycle SAR conversion for high speed and a fine 1-bit/cycle noise-shaping SAR conversion for high accuracy. The coarse conversion is performed by both voltage and time comparison for low power consumption. A redundancy after the coarse conversion corrects the error caused by a jitter noise during the time comparison. Additionally, a mismatch error between signal and reference paths is eliminated with the help of a tail-current-sharing comparator. The proposed ADC was designed in a 28 nm CMOS process, and the simulation result shows a 68.2 dB signal-to-noise distortion (SNDR) for a sampling rate of 480 MS/s and a bandwidth of 60 MHz with good energy efficiency.
Highlights
A successive approximation register (SAR) analog-to-digital converter (ADC) is wellknown to have high energy efficiency for medium bandwidth and moderate resolution
All simulations were performed with only the transistor level parasitic capacitance and resistance, which was information based on the P-Cell layout regression provided by the foundry to reduce the error between post-layout simulation and pre-layout simulation
The proposed ADC was designed to have an offset calibration circuit [13], which has 5 mV and 1 mV resolutions, so the coarse and fine comparators operate with offsets less than 5 mV and 1 mV, respectively
Summary
A successive approximation register (SAR) analog-to-digital converter (ADC) is wellknown to have high energy efficiency for medium bandwidth and moderate resolution. A noise-shaping SAR ADC is another kind of SAR-based hybrid ADC, and it performs oversampling and noise-shaping similar to a ∆Σ ADC [3] It can provide quite high resolution with very good energy efficiency; its bandwidth is often limited by oversampling and filter latency. The proposed ADC performs fast coarse 2-bit/cycle SAR conversion and does fine 1-bit/cycle SAR conversion with noise-shaping capability for high resolution. This approach can mitigate the trade-off between resolution and speed, as, which shows the achievable bandwidth of SAR-based ADCs versus signal-to-noise and distortion ratio (SNDR). The proposed ADC can achieve high resolution as well as high sampling rate compared with conventional SAR-based ADCs. The proposed 2--1-bit/cycle noise-shaping SAR ADC performs fast and coarse 2-bit/cycle SAR conversion first.
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