A fully dynamic third-order EF-CIFF noise-shaping SAR ADC with NTF zeros optimization and passive integration

Abstract

In this paper, a third-order noise-shaping successive approximation register (NS-SAR) analog-to-digital converter (ADC) is proposed which is simple and fully dynamic. A passive integrator is utilized in the feed-forward (FF) path of a second-order NS-SAR ADC with 2nd-order error-feedback (EF) filter to reduce the effect of inband quantization and comparator noise. The integrator implements a passive gain of 4x to make up its loss arising from the charge sharing between the integrator and digital-to-analog converter capacitors at the integration phase. Another advantage of the proposed structure is employing a simple low noise and low power one-input pair comparator unlike many published NS-SAR ADCs which use a comparator with multi-input pairs leading to enhanced comparator input-referred noise and power consumption. In this work, the zeros of the noise transfer function are optimized to enhance inband noise suppression. The proposed ADC is designed at circuit level using 0.18 μm TSMC CMOS technology with Cadence Virtuoso tool. The oversampling ratio, sampling frequency, and bandwidth are 8, 2.5 MS/s, and 156.25 kHz, respectively. According to the detailed post-layout simulation results, the achieved signal-to-noise and distortion ratio of the simulated ADC is 83.1 dB with 70.3 µW power consumption from a 1.1 V supply.