Time-interleaved Noise-shaping SAR ADC based on CIFF Architecture with Redundancy Error Correction Technique

Abstract

A time-interleaved noise-shaping (TINS) successive approximation register (SAR) analog-to-digital converter (ADC) based on the cascade of integrators with feed-forward (CIFF) architecture can achieve a high resolution and wide bandwidth with a high energy efficiency. Because it does not use the summation pre-amplifier, the energy efficiency obtained using the proposed ADC is higher than that of the TINS-SAR ADC based on the error-feedback (EF) architecture. In addition, the proposed ADC uses only one final residue sampling capacitor, and thus, the complexity of the circuit is reduced. The proposed ADC is implemented in a 65-nm CMOS process. According to the post-layout simulation result, a signal to noise and distortion ratio (SNDR) of 69.2 dB can be obtained for a sampling rate of 800 MS/s and bandwidth of 100 MHz with a high energy efficiency.