A 12 Bit 500 MS/s Sub-2 Radix SAR ADC for a Time-Interleaved 8 GS/s ADC in 28 nm CMOS

Abstract

This paper presents the design of a subsampling wideband 500 MS/s 12 Bit successive-approximation-register (SAR) analog-to-digital converter (ADC) with sub-2 radix split- capacitor array (SCA). The presented ADC is designed as a sub-ADC for a sample-and-hold-less (SAH-less) 8 GS/s time-interleaved (TI) ADC. In addition to the required 16 ADC channels, two additional SAR lanes enable pseudorandom binary sequence (PRBS)-driven channel scrambling. A 1.81 radix is used to achieve 12 Bit settling accuracy withing 70 ps. Extra scaling capacitors in the SCA enable SAR reference voltage levels near the supply rails, significantly reducing the SCA switch sizes. The necessity of a comparator latch reset phase is eliminated at the cost of higher comparator power consumption by the adoption of a loop-unrolled comparator improving the SAR loop timing. Top-plate charge kickback into the input buffer, a challenge that occurs within TI ADCs, is largely eliminated by implementing an additional reset phase within the SAR algorithm and the use of a boosted input T-switch. SCA and time-interleaved channel mismatch effects are addressed by calibrating each sub-ADC to an extra reference-ADC. The industry grade ADC design, achieves a spurious free dynamic range (SFDR) of 72 dB and signal to noise and distortion ratio (SNDR) of 54 dB across the entire 4 GHz frequency range. Designed in a 28 nm CMOS process, each sub-ADC consumes 33 mW from 1.8 V and 1V. The input buffer frontend uses supply voltages of 2.5 V and -1.3 V. The overall power consumption of the overall TI ADC is 3 W.