Abstract

Ultra-wideband (UWB) wireless communication is prospering as a powerful partner of the Internet-of-things (IoT). Due to the ongoing development of UWB wireless communications, the demand for high-speed and medium resolution analog-to-digital converters (ADCs) continues to grow. The successive approximation register (SAR) ADCs are the most powerful candidate to meet these demands, attracting both industries and academia. In particular, recent time-interleaved SAR ADCs show that multi-giga sample per second (GS/s) can be achieved by overcoming the challenges of high-speed implementation of existing SAR ADCs. However, there are still critical issues that need to be addressed before the time-interleaved SAR ADCs can be applied in real commercial applications. The most well-known problem is that the time-interleaved SAR ADC architecture requires multiple sub-ADCs, and the mismatches between these sub-ADCs can significantly degrade overall ADC performance. And one of the most difficult mismatches to solve is the sampling timing skew. Recently, research to solve this timing-skew problem has been intensively studied. In this paper, we focus on the cutting-edge timing-skew calibration technique using a window detector. Based on the pros and cons analysis of the existing techniques, we come up with an idea that increases the benefits of the window detector-based timing-skew calibration techniques and minimizes the power and area overheads. Finally, through the continuous development of this idea, we propose a timing-skew calibration technique using a comparator offset-based window detector. To demonstrate the effectiveness of the proposed technique, intensive works were performed, including the design of a 7-bit, 2.5 GS/s 5-channel time-interleaved SAR ADC and various simulations, and the results prove excellent efficacy of signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of 40.79 dB and 48.97 dB at Nyquist frequency, respectively, while the proposed window detector occupies only 6.5% of the total active area, and consumes 11% of the total power.

Highlights

  • The fourth industrial revolution is upon us

  • The window detector successive approximation register (SAR) analog-to-digital converters (ADCs) has a similar structure to sub-ADCs, except for the input cross-coupled comparators, which are used for window detection

  • Compared with previous works [20,22,23], the proposed circuit does not require the additional calibration to adjust the window width, thanks to its resistance to PVT variations. Because it requires only one comparison cycle, eliminating the need for the extra dummy-successive approximation register register analog-to-digital analog-to-digital converters (SAR ADC) to compensate for input impedance variations

Read more

Summary

Introduction

The fourth industrial revolution is upon us. Internet-of-things (IoT), big data analytics, and artificial intelligence (AI) are the representative leading-edge technologies that serve as enablers and facilitators of this revolution. Even if the SAR ADCs are designed to be relatively high speed, the power efficiency tends to be faded because power-hungry comparators and fast capacitive-digital-to-analog converter (CDAC) settling time are required. To enable high-speed ADC designs while maintaining the power-efficient advantage, researches to apply the time-interleaved architecture to the SAR ADC have been intensively studied [5,15,16,17,18,19,20,21,22,23].

Signal-to-noise
A Reviewtechniques is the statistic-based scheme proposed
Proposed
Block time-interleaved SAR
Comparator
Control
Timing-Skew Calibration Algorithm
Results
G Input cross-coupled comparators
16. Differential
Conclusions
Full Text
Published version (Free)

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call