Nanoscale CMOS Technology Research Articles

A Novel Chaotic Neural Network Using Memristive Synapse with Applications in Associative Memory

Chaotic Neural Network, also denoted by the acronym CNN, has rich dynamical behaviors that can be harnessed in promising engineering applications. However, due to its complex synapse learning rules and network structure, it is difficult to update its synaptic weights quickly and implement its large scale physical circuit. This paper addresses an implementation scheme of a novel CNN with memristive neural synapses that may provide a feasible solution for further development of CNN. Memristor, widely known as the fourth fundamental circuit element, was theoretically predicted by Chua in 1971 and has been developed in 2008 by the researchers in Hewlett‐Packard Laboratory. Memristor based hybrid nanoscale CMOS technology is expected to revolutionize the digital and neuromorphic computation. The proposed memristive CNN has four significant features: (1) nanoscale memristors can simplify the synaptic circuit greatly and enable the synaptic weights update easily; (2) it can separate stored patterns from superimposed input; (3) it can deal with one‐to‐many associative memory; (4) it can deal with many‐to‐many associative memory. Simulation results are provided to illustrate the effectiveness of the proposed scheme.

Novel radiation hardened latch design considering process, voltage and temperature variations for nanoscale CMOS technology

As CMOS technology is scaled down, the supply voltage and gate capacitance are reduced, which results in the reduction of charge storing capacity at each node and increase of the susceptibility to external noise in radiation environments. The traditional error tolerant circuit design methods provide very limited protection against the environment noise for storage cells such as latches and memories. In this paper, a novel hardened latch design is proposed and compared with the previous hardened latch designs using 32 nm technology node. Extensive simulation results using HSPICE are reported to show that the proposed hardened latch design achieves 15× improvement of critical charge (Qcrit) with comparable cost in terms of speed and power compared to the most up to date hardened latch design. Moreover, PVT variations have great impact on the reliability of hardened circuit. The proposed latch circuit is also evaluated with the presence of PVT variations and demonstrates higher robustness than other considered robust latch under severe PVT variation condition.

Design and test challenges in Nano-scale analog and mixed CMOS technology

Design and test challenges in Nano-scale analog and mixed CMOS technology

Overview on ESD Protection Designs of Low-Parasitic Capacitance for RF ICs in CMOS Technologies

CMOS technology has been widely used to implement radio-frequency integrated circuits (RF ICs). However, the thinner gate oxide in nanoscale CMOS technology seriously degrades the electrostatic discharge (ESD) robustness of RF ICs. Therefore, on-chip ESD protection designs must be added at all input/output pads in RF circuits against ESD damages. To minimize the impacts from ESD protection circuit on RF performances, ESD protection circuit at input/output pads must be carefully designed. An overview on ESD protection designs with low parasitic capacitance for RF circuits in CMOS technology is presented in this paper. The comparisons among these ESD protection designs are also discussed. With the reduced parasitic capacitance, ESD protection circuit can be easily combined or co-designed with RF circuits. As the operating frequencies of RF circuits increase, on-chip ESD protection designs for RF applications will continuously be an important design task.

Advanced strain engineering for state-of-the-art nanoscale CMOS technology

The introduction and advancement of strain engineering has been one of the most critical features for the state-of-the-art nanoscale CMOS transistors. This paper provides an overview of the major strain engineering techniques that have remarkably re-shaped the advanced CMOS transistor architecture, including embedded SiGe (eSiGe), embedded Si:C (eSi:C), stress memorization technique (SMT), dual stress liners (DSL), and stress proximity technique (SPT). The advent of high-K/metal-gate (HKMG) also brings in additional strain benefit with its metal gate stressor (MGS) and replacement gate (RMG) process. Strain engineering continues to evolve and will remain to be one of the key performance enablers for the future generation of CMOS technologies.

Variability in nanoscale CMOS technology

Moore’s Law technology scaling has improved VLSI performance by five orders of magnitude in the last four decades. As advanced technologies continue the pursuit of Moore’s Law, a variety of challenges will need to be overcome. One of these challenges is management of process variation. This paper discusses the importance of process variation in modern CMOS transistor technology, reviews front-end variation sources, presents device and circuit variation measurement techniques (including circuit and SRAM data from the 32 nm node), and compares recent intrinsic transistor variation performance from the literature.

Analog IC Design in Ultra-Thin Oxide CMOS Technologies With Significant Direct Tunneling-Induced Gate Current

Recent studies have shown that manufacturing costs and design complexities may delay the widespread use of high-κ/metal gate nanoscale CMOS technologies. This implies that traditional (non-high-κ/non-metal gate) ultra-thin oxide technologies will remain active due to economic factors for longer periods of time. Direct tunneling is a significant source of MOSFET gate current in these technologies. Its presence fundamentally alters MOSFET functionality by invalidating the simplifying design assumption of infinite gate resistance. Analog circuit solutions to its problems do not exist in the literature. This paper proposes design solutions that attempt to minimize, balance, and cancel the negative effects of direct tunneling on analog design in traditional ultra-thin oxide CMOS technologies. The proposed solutions re quire only ultra-thin oxide devices and are investigated in a 65-nm CMOS technology with a nominal V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> of 1 V and a physical oxide thickness of 1.25 nm.

Design considerations for high-data-rate chip interconnect systems

Over the past decade, data rates for electrical interconnects in interchip communications systems have experienced a dramatic increase from <;1 Gb/s to 10 Gb/s and beyond to keep up with ever increasing demands for more I/O bandwidth from modern high-capacity storage, networking, and data processing systems. This article presents an overview of the high-data-rate chip interconnect design space, including a short description of the channel, line equalization architecture, and design considerations for key I/O core subsystems realized in nanoscale CMOS technology.

A Phase-Locked Loop With Background Leakage Current Compensation

A background compensation method is presented to compensate the leakage current of MOS capacitors for phase-locked loops (PLLs) in nanoscale CMOS technology. A leakage detection circuit is used to adjust a voltage-controlled current source to compensate the leakage current. This PLL has been fabricated in 65-nm CMOS technology. With the background leakage current compensation, the measured peak-to-peak and rms jitters of this PLL at 1 GHz are 36 and 4.54 ps, respectively. Its power consumption is 8.4 mW for a 1.2-V supply voltage.

An interconnect width and spacing optimization model considering scattering effect

As the feature size of the CMOS integrated circuit continues to shrink, the more and more serious scattering effect has a serious impact on interconnection performance, such as delay and bandwidth. Based on the impact of the scattering effect on latency and bandwidth, this paper first presents the quality-factor model which optimises latency and bandwidth effectively with the consideration of the scattering effect. Then we obtain the analytical model of line width and spacing with application of curve-fitting method. The proposed model has been verified and compared based on the nano-scale CMOS technology. This optimisation model algorithm is simple and can be applied to the interconnection system optimal design of nano-scale integrated circuits.

Linear low voltage nano-scale CMOS transconductor

This paper presents a high linearity MOSFET-only transconductor based on differential structures. While a precise BSIM4 transistor model is introduced through analysis, the linearity can be improved by mobility compensation techniques as the device size is scaled down in the nano-scale CMOS technology. When the compensation utilizes transistors in subthreshold region, rather than the transistors in saturation region, the value of transconductance can be maintained. The circuit is fabricated in TSMC 0.18-μm CMOS process. The measurement results show 18 dB improvement of the proposed version, and 65 dB HD3 can be achieved for a 2.1 MHz 700 mVpp differential input. The static power consumption under 1-V power supply voltage is 183 μW. Measurement results demonstrate the agreement with theoretical analyses.

An Interconnect-Line-Size Optimization Model Considering Scattering Effect

Based on the impact of the scattering effect on latency and bandwidth, this letter presents the quality-factor model that optimizes latency and bandwidth effectively with consideration of the scattering effect. Then, we get the optimization analytical model with target interconnect linewidth and line spacing by the curve-fitting method. The proposed model has been verified and compared for nanoscale CMOS technology. The optimization model is simple, and we can apply it to the interconnect system optimal design of nano-CMOS integrated circuits.

Reliability Implications of Bias-Temperature Instability in Digital ICs

Bias temperature instability (BTI) is one of the major reliability challenges in nanoscale CMOS technology. This article investigates the severity of such degradation in logic and memory circuits. The simulation results reveal that BTI poses severe constraints on reliable memory design, especially in the presence of random process variations.

Feasibility Study of Analogue and Digital Temperature Sensors in Nanoscale CMOS Technologies

The downscaling of CMOS technology gives rise to a myriad of nanoscale effects. At the same time, power density and thus heat generation increases. The aim of this paper is to evaluate the feasibility of both analogue and digital temperature sensors in nanoscale CMOS using the Berkeley Predictive Technology Model (BPTM) for 65nm. For the oscillator-based digital sensor presented, a sensitivity of 1.86MHz/{degree sign}C is achieved. The analogue sensor achieves a sensitivity of 1.7mV/{degree sign}C.

Impact of Gate Leakage on Performances of Phase-Locked Loop Circuit in Nanoscale CMOS Technology

In the nanoscale CMOS technology, the thin gate oxide causes large gate-tunneling leakage. In this brief, the influence of gate-tunneling leakage in the MOS capacitor (used in the loop filter) on the circuit performance of the phase-locked loop (PLL) in the nanoscale CMOS technology has been investigated and analyzed. The basic PLL with a second-order loop filter is used to observe the impact of gate-tunneling leakage on the performance degradation of the PLL in a 90-nm CMOS process. The MOS capacitors with different oxide thicknesses are used to investigate their impact on the PLL performance. The locked time, static phase error, and jitter of the second-order PLL are found to be degraded by the gate-tunneling leakage of the MOS capacitor used in the loop filter.

A Zero-IF 60 GHz 65 nm CMOS Transceiver With Direct BPSK Modulation Demonstrating up to 6 Gb/s Data Rates Over a 2 m Wireless Link

This paper presents a directly modulated, 60 GHz zero-IF transceiver architecture suitable for single-carrier, low-power, multi-gigabit wireless links in nanoscale CMOS technologies. This mm-wave front end architecture requires no upconversion of the baseband signals in the transmitter and no analog-to-digital conversion in the receiver, thus minimizing system complexity and power consumption. All circuit blocks are realized using sub-1.0 V topologies, that feature only a single high-frequency transistor between the supply and ground, and which are scalable to future 45 nm, 32 nm, and 22 nm CMOS nodes. The transceiver is fabricated in a 65 nm CMOS process with a digital back-end. It includes a receiver with 14.7 dB gain and 5.6 dB noise figure, a 60 GHz LO distribution tree, a 69 GHz static frequency divider, and a direct BPSK modulator operating over the 55-65 GHz band at data rates exceeding 6 Gb/s. With both the transmitter and the receiver turned on, the chip consumes 374 mW from 1.2 V which reduces to 232 mW for a 1.0 V supply. It occupies 1.28 times 0.81 mm2. The transceiver and its building blocks were characterized over temperature up to 85deg C and for power supplies down to 1 V. A manufacturability study of 60 GHz radio circuits is presented with measurements of transistors, the low-noise amplifier, and the receiver on slow, typical, and fast process splits. The transceiver architecture and performance were validated in a 1-6 Gb/s 2-meter wireless transmit-receive link over the 55-64 GHz range.

Feedback Biasing in Nanoscale CMOS Technologies

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This work rediscovers the attractiveness of feedback biasing when applied to circuits designed in nanoscale CMOS technologies. It is shown that very compact amplifiers can be obtained by utilizing a type of biasing that imposes minimal area overhead. We discuss how the undesired features of the nanoscale CMOS technologies actually help in the revival of this simple biasing method in newer technology generations. The measurement results of prototyped common-source (CS) amplifiers utilizing feedback biasing for application in medical ultrasound imaging systems are presented in this brief. The proposed feedback biasing is also suitable for amplifying signals from high-impedance sources that pose challenges on maintaining high input impedance for the voltage amplifiers while maintaining a very low input capacitance value. Measurements show that the proposed amplifier achieves a voltage gain of 28 dB, an output noise power spectral density of 0.11 <formula formulatype="inline"><tex Notation="TeX">$(\mu\hbox{V})^{2}/ \hbox{Hz}$</tex></formula> at center-frequency, and a total harmonic distortion of <formula formulatype="inline"> <tex Notation="TeX">$-$</tex></formula>30 dB, with the full-scale output at 30 MHz, while drawing 120 <formula formulatype="inline"> <tex Notation="TeX">$\mu\hbox{A}$</tex></formula> from a 1-V power supply. The amplifiers were fabricated in 90-nm CMOS technology and measured to be just <formula formulatype="inline"><tex Notation="TeX">$20\ \mu\hbox{m} \times 10\ \mu\hbox{m}$</tex></formula>. </para>

Modified Model for Settling Behavior of Operational Amplifiers in Nanoscale CMOS

An accurate time-domain model for the settling behavior of folded-cascode operational amplifiers is presented. Using a velocity-saturation model for MOS transistors makes the proposed model suitable for nanoscale CMOS technologies. Both linear and nonlinear settling regimes and their combination are considered. Transistor-level HSPICE simulation results of a fully differential single-stage folded-cascode amplifier using BSIM4v3 models of a standard 90-nm CMOS process are presented to verify the accuracy of the proposed models.

Analysis of Novel Helmholtz-inductively Coupled Plasma Source and Its Application for Nano-Scale MOSFETs

A novel Helmholtz coil inductively coupled plasma (H-ICP) etcher is proposed and characterized for deep nanoscale CMOS technology. Various hardware tests are performed while varying key parameters such as distance between the top and bottom coils, the distance between the chamber ceiling and the wafer, and the chamber height in order to determine the optimal design of the chamber and optimal process conditions. The uniformity was significantly improved by applying the optimum conditions. The plasma density obtained with the H-ICP source was about 5×10/cm, and the electron temperature was about 2–3 eV. The etching selectivity for the poly-silicon gate versus the ultra-thin gate oxide was 482:1 at 10 sccm of HeO2. The proposed H-ICP was successfully applied to form multiple 60-nm poly-silicon gate layers.

Utilizing Process Variations for Reference Generation in a Flash ADC

This brief presents an experimental study on how to take advantage of the increasing process variations in nanoscale CMOS technologies to achieve small and low-power high-speed analog-to-digital converters (ADCs). Particularly, the need for a reference voltage generation network has been eliminated in a 4-bit Flash ADC in 90-nm CMOS, with small-sized comparators. The native comparator offsets, resulting from the process-variation-induced mismatch, are used as the only source of reference levels, and redundancy is used to acquire the desired resolution. The measured performance of the 1.5-GS/s ADC is comparable to traditional state-of-the art ADCs and dissipates 23 mW.