Design considerations for high-data-rate chip interconnect systems

Abstract

Over the past decade, data rates for electrical interconnects in interchip communications systems have experienced a dramatic increase from <;1 Gb/s to 10 Gb/s and beyond to keep up with ever increasing demands for more I/O bandwidth from modern high-capacity storage, networking, and data processing systems. This article presents an overview of the high-data-rate chip interconnect design space, including a short description of the channel, line equalization architecture, and design considerations for key I/O core subsystems realized in nanoscale CMOS technology.