Feasibility Study of Analogue and Digital Temperature Sensors in Nanoscale CMOS Technologies

Abstract

The downscaling of CMOS technology gives rise to a myriad of nanoscale effects. At the same time, power density and thus heat generation increases. The aim of this paper is to evaluate the feasibility of both analogue and digital temperature sensors in nanoscale CMOS using the Berkeley Predictive Technology Model (BPTM) for 65nm. For the oscillator-based digital sensor presented, a sensitivity of 1.86MHz/{degree sign}C is achieved. The analogue sensor achieves a sensitivity of 1.7mV/{degree sign}C.