Nanoscale CMOS Technology Research Articles

Low power, high speed Schmitt trigger using SVL technique in nanoscale CMOS technology

Schmitt trigger device is mostly used in analogue and digital circuit as a wave-shaping device to resolve the noise problem, widely used to drive the load with fast switching low-power loss and low-power supply. Conventional Schmitt trigger provides more leakage power, so 4T Schmitt trigger overcomes this problem by using the Self-Controllable Voltage Level (SVL) techniques. The main purpose of this paper is to present the performance factor of Schmitt trigger by applying U-SVL and L-SVL and both technique. The simulation results perform in cadence tool and reported that static power (3.98 fW), dynamic power (38.04 pW), propagation delay (6.13 psec), hysteresis width (0.877 V), voltage gain (30.03 dB), periodic jitter (80 ns), frequency jitter (24.26 kHz), efficiency (63.06%), spectral power (5.388 aW), transconductance (7.17 × 10−14 S) and the total leakage power of individual transistors (1.17 pW) improve using both U-SVL and L-SVL techniques simultaneously with nanoscale measurement with supply voltage Vdd=0.7 V.

Design of ESD Protection Device for <inline-formula> <tex-math notation="LaTeX">$K\!/\!Ka$ </tex-math> </inline-formula>-Band Applications in Nanoscale CMOS Process

An inductor-assisted silicon-controlled rectifier (LASCR) device is proposed to protect the gigahertz ICs in nanoscale CMOS technologies from electrostatic discharge (ESD) damages. The LASCR with the assistance of inductor can provide the bidirectional ESD current paths and fine-tune the high-frequency performances. Each LASCR test device has been implemented in a compact size of $\sim 100\times 100~\mu \text{m}^{2}$ . The LASCR test devices have been successfully verified in a silicon chip to achieve 4–7.5 kV human-body-model ESD robustness with 1–3-dB loss in $K/Ka$ -band (18–40 GHz). With the better performances, the proposed ESD protection device is very suitable for $K/Ka$ -band applications.

A 100-MHz Breakdown-Resilient Power Converter With Fully Monolithic Implementation on Nanoscale CMOS Process

A monolithic switched-capacitor power converter is designed in the nanoscale CMOS technology, employing a two-stage system architecture to mitigate overvoltage breakdown risk. The efficiency impact of various parasitic components is analyzed for design optimization on both the topology level and the device level. An external capacitorless low-dropout regulator with a wide bandwidth and a high power supply rejection ratio is introduced, removing high-frequency ripples and enabling a fast load transient response. The proposed design was implemented with the 180-nm CMOS process. At a switching frequency of 100 MHz, it regulates $V_\mathrm{out} $ at 0.8 V, with a maximum power efficiency of 60%. When the load current switches between 1.5 and 15 mA, $V_\mathrm{out} $ responds within 45 ns, with a voltage droop below 45 mV.

Compact Design of Low Power Standard Ternary Inverter Based on OFF-State Current Mechanism Using Nano-CMOS Technology

We propose a novel standard ternary inverter (STI) based on nanoscale CMOS technology for a compact design of multivalued logic. Using the gate bias independent OFF-state mechanisms of junction band-to-band tunneling (BTBT), tristate STI operation has been demonstrated in the conventional binary CMOS inverter by TCAD device and mixed-mode circuit simulation with 32-nm high- $\kappa $ /metal-gate technology. Through analytical device modeling on BTBT and subthreshold current, static noise margin (SNM), off-leakage variation (OLV), and operation voltage ( $V_{\mathrm {DD}})$ scaling limits of STI have been investigated. The typical SNM is 200 mV and the variability of the intermediate level ( $\Delta V_{\mathrm {OM}}\sim 50$ mV) from OLV can be allowable into the worst SNM (>100 mV) of STI operation at $V_{\mathrm {DD}}= 1$ V. Exponentially reduced BTBT off-leakage around minimum $V_{\mathrm {DD}}\sim 0.1$ V is promising for ultimate low-power application of our STI.

Very low thermal drift precision virtual voltage reference

A digital-based, process-supply-and-temperature independent voltage reference suitable to nanoscale CMOS technologies, which exploits the recently proposed ‘virtual reference’ concept to achieve a very low thermal drift, is presented. Its performance is assessed on the basis of simulations and experiments carried out on a microcontroller-based, proof-of-concept prototype and is compared with state-of-the-art integrated analogue and digital voltage references. A simulated (measured) thermal drift as low as 1 ppm/°C (5 ppm/°C) in the temperature range −40/+140°C (−10/+100°C) is reported.

A nature-inspired firefly algorithm based approach for nanoscale leakage optimal RTL structure

Optimization of leakage power is essential for nanoscale CMOS (nano-CMOS) technology based integrated circuits for numerous reasons, including improving battery life of the system in which they are used as well as enhancing reliability. Leakage optimization at an early stage of the design cycle such as the register-transfer level (RTL) or architectural level provides more degrees of freedom to design engineers and ensures that the design is optimized at higher levels before proceeding to the next and more detailed phases of the design cycle. In this paper, an RTL optimization approach is presented that targets leakage-power optimization while performing simultaneous scheduling, allocation and binding. The optimization approach uses a nature-inspired firefly algorithm so that large digital integrated circuits can be effectively handled without convergence issues. The firefly algorithm optimizes the cost of leakage delay product (LDP) under various resource constraints. As a specific example, gate-oxide leakage is optimized using a 45nm CMOS dual-oxide based pre-characterized datapath library. Experimental results over various architectural level benchmark integrated circuits show that average leakage optimization of 90% can be obtained. For a comparative perspective, an integer linear programming (ILP) based algorithm is also presented and it is observed that the firefly algorithm is as accurate as ILP while converging much faster. To the best of the authors׳ knowledge, this is the first ever paper that applies firefly based algorithms for RTL optimization.

New Assessment Methodology Based on Energy–Delay–Yield Cooptimization for Nanoscale CMOS Technology

A new technology assessment methodology is proposed to simultaneously evaluate circuit-level energy, delay, and yield under realistic device operation theme through Monte Carlo analysis. Given any yield constraints, this new methodology can maximize the circuit energy efficiency without overdesign. It provides a method to quantify the tradeoff between energy–delay (ED) and yield. The proposed method is proved to be efficient especially for low power circuit applications compared with ED-only approach. Taking 14-nm FinFET design, for example, the impacts of major variation sources are analyzed for different circuit applications, showing a different trend from the ED-only approach. In addition, the methodology is also extended to include the impacts of reliability issues. A desired design strategy is found to balance the design merits and circuit reliability. The proposed methodology is helpful for technology assessment and early stage circuit design and planning.

A Self-Recoverable, Frequency-Aware and Cost-Effective Robust Latch Design for Nanoscale CMOS Technology

A Self-Recoverable, Frequency-Aware and Cost-Effective Robust Latch Design for Nanoscale CMOS Technology

Via Diode in Cu Backend Process for 3D Cross-Point RRAM Arrays

In this paper, a fully logic compatible via diode is developed for high-density resistive random access memory (RRAM) array applications. This novel via diode is realized by advanced 28nm CMOS technology with Cu damascene via. The device is stacked between a top Cu via and a bottom Cu metal with a composite layer of TaN/TaON based dielectric film. An asymmetric current-voltage characteristic in this MIM structure provides a forward/reverse current ratio up to 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> . In a cross-point RRAM array, the suppression of sneak current path by incorporating this via diode enables array size to be greatly expended. Via diode provides an excellent solution for high-density embedded nonvolatile memory applications in the nano-scale CMOS technology.

Maximizing Yield per Area of Highly Parallel CMPs Using Hardware Redundancy

The manufacturing yield of chip multiprocessors (CMPs) has become a significant problem as more transistors are integrated onto a single die and the defect rate keeps increasing for “end-of-Moore” nano-scale CMOS technologies. Since such CMP designs usually have significant structural symmetry, adding spare copies to these should be an effective method for increasing yield per area, as is the case for memories. However, a systematic approach to add spare copies to optimize CMP yield per area has never been developed, primarily due to the lack of: 1) a general model of CMP architectures and 2) a practically-useable model for computing areas of chip versions with different configurations of spare copies. This paper develops such models and, in conjunction with a systematic approach for enumerating a wide range of spare configurations, uses these to compute the area overhead and yield for each configuration. In particular, this paper proposes a general spare cores sharing technique to maximize yield per area of any CMP by efficiently traversing the design space for adding spare cores. Experimental results show that the advantage of the proposed approach over traditional approaches increases with continued technology scaling. Specifically, the proposed approach achieves \(2\times \) yields per area over previous approaches for 32 nm and 22 nm technologies. Also, the obtained yield per area values provided by our approach are around 70% of that obtained for the ideal scenario where defect density is zero and no redundancy is added.

Memristor-based cellular nonlinear/neural network: design, analysis, and applications.

Cellular nonlinear/neural network (CNN) has been recognized as a powerful massively parallel architecture capable of solving complex engineering problems by performing trillions of analog operations per second. The memristor was theoretically predicted in the late seventies, but it garnered nascent research interest due to the recent much-acclaimed discovery of nanocrossbar memories by engineers at the Hewlett-Packard Laboratory. The memristor is expected to be co-integrated with nanoscale CMOS technology to revolutionize conventional von Neumann as well as neuromorphic computing. In this paper, a compact CNN model based on memristors is presented along with its performance analysis and applications. In the new CNN design, the memristor bridge circuit acts as the synaptic circuit element and substitutes the complex multiplication circuit used in traditional CNN architectures. In addition, the negative differential resistance and nonlinear current-voltage characteristics of the memristor have been leveraged to replace the linear resistor in conventional CNNs. The proposed CNN design has several merits, for example, high density, nonvolatility, and programmability of synaptic weights. The proposed memristor-based CNN design operations for implementing several image processing functions are illustrated through simulation and contrasted with conventional CNNs. Monte-Carlo simulation has been used to demonstrate the behavior of the proposed CNN due to the variations in memristor synaptic weights.

On the Design of Power-Rail ESD Clamp Circuits With Gate Leakage Consideration in Nanoscale CMOS Technology

CMOS technology has been widely used to produce many integrated circuits. However, the thinner gate oxide in nanoscale CMOS technology seriously increases the difficulty of electrostatic discharge (ESD) protection design. The power-rail ESD clamp circuit has been the key circuit to perform the whole-chip ESD protection scheme. Some ESD detection circuits were developed to trigger on ESD devices across the power rails to quickly discharge ESD current away from the internal circuits. Therefore, on-chip ESD protection circuits must be designed with the consideration of standby leakage to minimize the power consumption and the possibility of malfunction to normal circuit operation. The design of power-rail ESD clamp circuits with low standby leakage current and high efficiency of layout area in nanoscale CMOS technology is reviewed in this paper. The comparisons among those power-rail ESD clamp circuits are also discussed.

Low-Power Multiport SRAM With Cross-Point Write Word-Lines, Shared Write Bit-Lines, and Shared Write Row-Access Transistors

This brief proposes one-write-one-read (1W1R) and two-write-two-read (2W2R) multiport (MP) SRAMs for register file applications in nanoscale CMOS technology. The cell features a cross-point Write word-line structure to mitigate Write Half-Select disturb and improve the static noise margin (SNM). The Write bit-lines (WBLs) and Write row-access transistors are shared with adjacent bit-cells to reduce the cell transistor count and area. The scheme halves the number of WBL, thus reducing WBL leakage and power consumption. In addition, column-based virtual VSS control is employed for the Read stack to reduce the Read power consumption. Post-sim results show that the proposed scheme reduces both Write/Read current consumption by over 30% compared with the previous MP structure. The proposed scheme is demonstrated and validated by an 8-Kb 2W2R SRAM test chip fabricated in TSMC 40-nm CMOS technology.

Design of an NoC Interface Macrocell with Hardware Support of Advanced Networking Functionalities

This paper presents the design and the characterization in nanoscale CMOS technology of a Network Interface (NI) for on-chip communication infrastructure with hardware support of advanced networking functionalities: store &#x0026; forward (S&#x0026;F) transmission, error management, power management, ordering handling, security, QoS management, programmability, end-to-end protocol interoperability, remapping. The design has been conceived as a scalable architecture: The advanced features can be added on top of a basic NI core implementing data packetization and conversion of protocols, frequency and data size between the connected Intellectual Property (IP) core and the on chip network. The NI can be configured to reach the desired tradeoff between supported services and circuit complexity.

Investigations on Line-Edge Roughness (LER) and Line-Width Roughness (LWR) in Nanoscale CMOS Technology: Part I–Modeling and Simulation Method

In this paper, the correlation between line-edge roughness (LER) and line-width roughness (LWR) is investigated. Based on the characterization methodology of auto-correlation functions (ACF), a new theoretical model of LWR is proposed, which indicates that the LWR ACF is composed of two parts: one involves LER information; the other involves the cross-correlation of the two edges. Additional characteristic parameters for LER/LWR are proposed to represent the missing cross-correlation information in conventional approaches of LER/LWR description, other than LER/LWR amplitude and auto-correlation length. An improved simulation method for correlated LERs is also proposed, which can provide helpful guidelines for the characterization, modeling, and the optimization of LER/LWR in nanoscale CMOS technology. The experimental results and device simulation results are discussed in detail in the part II of this paper.

Coupling induced soft error mechanisms in nanoscale CMOS technologies

Due to scaling induced effects, CMOS circuits become increasingly more sensitive to transient pulses caused by single event (SE) particles. Researchers mostly considered SE transients as the main cause for combinational logic (CL) related radiation-induced soft errors. However, for high-reliability applications such as avionics, military and medical applications, additional sources such as SE induced soft delays, clock jitters, false clock pulses and crosstalk effects need to be included in soft-error reliability analysis. As technologies advance, coupling effects among interconnects increasingly cause SE transients to contaminate electronically unrelated circuit paths, which can in turn increase the "SE susceptibility" of CMOS circuits. This work focuses on such coupling induced soft error mechanisms in CL, namely the SE crosstalk noise and delay effects. An attempt has been made to compare SE crosstalk noise and SE transient effects, and crosstalk contribution to soft error rate has been examined. In addition, the SE induced coupling delay effect has been studied and compared to radiation induced soft delay effect for various technologies. Results show that, in newer technologies, the SE coupling delay becomes quite comparable to soft delay effect, although caused indirectly by cross-coupling effects. In comparisons, the distributed nature of interconnects has been taken into account and results are demonstrated using HSPICE simulations with interconnect and device parameters derived in 130, 90 and 65 nm technologies.

Improved inverter‐based read‐out scheme for low‐power ISFET sensing array

The digital read-out scheme in an ion-sensitive field effect transistor (ISFET) sensing array is more advantageous when compared with the analogue counterpart because of its lower power consumption, smaller area and less susceptibility to environmental noise and parasitics. An improved read-out scheme is proposed in which each ISFET is stacked with a CMOS inverter to form a pH-to-time converter. The pH level of the solution regulates the strength of the ISFET, which in turn modulates the delay of the stacked inverter and hence the pulse width of the output signal. Simulation results using the 0.18 µm/2.5 V CMOS process show that the modulated pulse width changes linearly over a wide range of pH. The design achieves five orders of magnitude smaller leakage and 40% lower dynamic power consumption, while it requires only 50% of silicon area when compared with the conventional design. It is therefore more suitable for large ISFET arrays implemented in nano-scale CMOS technologies.

Investigations on Line-Edge Roughness (LER) and Line-Width Roughness (LWR) in Nanoscale CMOS Technology: Part II–Experimental Results and Impacts on Device Variability

In the part I of this paper, the correlation between line-edge roughness (LER) and line-width roughness (LWR) is investigated by theoretical modeling and simulation. In this paper, process-dependence of the correlation between LER and LWR is studied. The experimental results indicate that both Si Fin and nanowire have strongly correlated LER/LWR, and the cross-correlation of two edges depends on the fabrication process. Based on the improved simulation method proposed in the Part I of this paper, the impacts of correlated LER/LWR in the channel of double-gate devices are investigated. The results show that Vth distribution strongly relies on cross-correlation, and can exhibit non-Gaussian distribution and/or multipeak distribution, which enlarges the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> variation.

Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology

In this paper, a multi-level wordline driver scheme is presented to improve 6T-SRAM read and write stability. The proposed wordline driver generates a shaped pulse during the read mode and a boosted wordline during the write mode. During read, the shaped pulse is tuned at nominal voltage for a short period of time, whereas for the remaining access time, the wordline voltage is reduced to save the power consumption of the cell. This shaped wordline pulse results in improved read noise margin without any degradation in access time for small wordline load. The improvement is explained by examining the dynamic and nonlinear behavior of the SRAM cell. Furthermore, during the hold mode, for a short time (depending on the size of boosting capacitance), wordline voltage becomes negative and charges up to zero after a specific time that results in a lower leakage current compared to conventional SRAM. The proposed technique results in at least 2× improvement in read noise margin while it improves write margin by 3× for lower supply voltages than 0.7V. The leakage power for the proposed SRAM is reduced by 2% while the total power is improved by 3% in the worst case scenario for an SRAM array. The main advantage of the proposed wordline driver is the improvement of dynamic noise margin with less than 2.5% penalty in area. TSMC 65nm technology models are used for simulations.

Analyses and design of 95-GHz SoC CMOS radiometers for passive body imaging

Passive radiometry is a health-safe alternative to other imaging techniques conceived to be used on human beings for security screening or medical imaging applications. In this work we address a study on the feasibility of W-band passive radiometers in nano-scale CMOS technology for imaging applications. In particular, this study takes into account some of the most relevant aspects regarding the system-on-a-chip implementation, from system to circuit and technology limitations, with emphasis on the impact of the non-idealities of the detector on the overall system performances. Excluding the hardware differences between the investigated receiver architectures and their substantial implications, especially in case of array systems, the investigation shows how there is no a clear evidence to identify a priori the best performance receiver architecture, but it depends on the circuits, as well as operating frequency and technology.