A 100-MHz Breakdown-Resilient Power Converter With Fully Monolithic Implementation on Nanoscale CMOS Process

Abstract

A monolithic switched-capacitor power converter is designed in the nanoscale CMOS technology, employing a two-stage system architecture to mitigate overvoltage breakdown risk. The efficiency impact of various parasitic components is analyzed for design optimization on both the topology level and the device level. An external capacitorless low-dropout regulator with a wide bandwidth and a high power supply rejection ratio is introduced, removing high-frequency ripples and enabling a fast load transient response. The proposed design was implemented with the 180-nm CMOS process. At a switching frequency of 100 MHz, it regulates $V_\mathrm{out} $ at 0.8 V, with a maximum power efficiency of 60%. When the load current switches between 1.5 and 15 mA, $V_\mathrm{out} $ responds within 45 ns, with a voltage droop below 45 mV.