An output-capacitor-less low-dropout voltage regulator with high power supply rejection ratio and fast load transient response using boosted-input-transconductance structure

Abstract

This paper proposes an output-capacitor-less (OCL) low-dropout voltage regulator (LDO) with a novel boosted-input-transconductance input stage in the error amplifier (EA) to achieve high power supply rejection ratio (PSRR) as well as fast load transient response. Such input stage is realized by integrating the common-gate G m -cells with an input-transconductance boost structure. The proposed design is simulated with BSIM models in 65 nm CMOS technology. Simulation results exhibit a PSRR as high as 63 dB in the proposed design with fast load transient response of 1.9-μs undershoot settling time and 5-ps overshoot settling time when the load current (I L ) varies between 10 μA and 100 mA in 100 ns. The current efficiency of the OCL LDO reaches as high as 99.996% at the full load of 100 mA.