Variability in nanoscale CMOS technology

Abstract

Moore’s Law technology scaling has improved VLSI performance by five orders of magnitude in the last four decades. As advanced technologies continue the pursuit of Moore’s Law, a variety of challenges will need to be overcome. One of these challenges is management of process variation. This paper discusses the importance of process variation in modern CMOS transistor technology, reviews front-end variation sources, presents device and circuit variation measurement techniques (including circuit and SRAM data from the 32 nm node), and compares recent intrinsic transistor variation performance from the literature.