Nanoscale CMOS Technology Research Articles

CMOS IC Solutions for the 77 GHz Radar Sensor in Automotive Applications

This paper presents recent results on CMOS integrated circuits for automotive radar sensor applications in the 77 GHz frequency band. It is well demonstrated that nano-scale CMOS technologies are the best solution for the implementation of low-cost and high-performance mm-wave radar sensors since they provide high integration level besides supporting high-speed digital processing. The present work is mainly focused on the RF front-end and summarizes the most stringent requirements of both short/medium- and long-range radar applications. After a brief introduction of the adopted technology, the paper addresses the critical building blocks of the receiver and transmitter chain while discussing crucial design aspects to meet the final performance. Specifically, effective circuit topologies are presented, which concern mixer, variable-gain amplifier, and filter for the receiver, as well as frequency doubler and power amplifier for the transmitter. Moreover, a voltage-controlled oscillator for a PLL efficiently covering the two radar bands is described. Finally, the circuit description is accompanied by experimental results of an integrated implementation in a 28 nm fully depleted silicon-on-insulator CMOS technology.

LDAVPM: A Latch Design and Algorithm-Based Verification Protected Against Multiple-Node-Upsets in Harsh Radiation Environments

In deep nano-scale and high-integration CMOS technologies, storage circuits have become increasingly sensitive to charge-sharing-induced multiple-node-upsets (MNUs) that include double, triple and quadruple node-upsets. Currently, verifications for error-recovery of existing latches highly rely on EDA tools with complex error-injection combinations. In this paper, a latch design protected against MNUs in harsh radiation as well as an algorithm-based verification process are proposed. Due to the constructed redundant feedback loops, the latch can completely recover from any MNU. Algorithm-based verification and simulations both demonstrate the MNU recovery of the proposed latch. Simulation results demonstrate the low area overhead of the proposed latch compared with the only one existing of the same type.

A Novel Ultra Low-Voltage / Low-Power Rail-to-Rail Comparator Topology in Nanoscale CMOS Technology

A Novel Ultra Low-Voltage / Low-Power Rail-to-Rail Comparator Topology in Nanoscale CMOS Technology

A novel ultra low-voltage/low-power rail-to-rail comparator topology in nanoscale CMOS technology

The article addresses a novel topology of analog voltage comparator capable of processing the input voltage in rail-to-rail range. We propose two different innovative comparator topologies. One topology is employing a standard “gate-driven” (GD) control of MOS transistors and is designed in 65 nm CMOS technology. The other one, designed in 130 nm CMOS technology, uses rather unconventional “bulk-driven” (BD) control of active devices in the circuit. Each presented circuit topology has its own pros and cons. However, both are suitable and actually aimed for ultra low-voltage (ULV) and/or ultra low-power (ULP) applications. The proposed comparator designs have been extensively analyzed for robustness and parameter stability across all fabrication process corners, wide temperature range (from −20 °C to 85 °C) and for random process variations as well. Both presented comparator designs can reliably operate with power consumption in nano-watt range without any fuse trimming or calibration, as the proof of concept has been confirmed by measurements performed on chip prototypes.

Time-to-digital conversion techniques: a survey of recent developments

Time-to-digital converters (TDCs) are key components of time-mode circuits and enablers for digital processing of analog signals encoded in time. Since design of time-mode circuits facilitates replacing analog blocks with digital circuitry, TDCs pave the way to hardware-efficient and purely digital architectures in deep-submicron semiconductor technology. The design and implementation of modern TDCs is heterogeneous, shaped in multiple directions, and driven by CMOS process downscaling along with application demands. The substantial research effort is made in more intensive digital implementations, optimization of techniques for high resolution, increasing input range and linearity, reduced conversion time, power consumption and silicon area. The calibration and mismatch-tolerant, as well as anti-PVT-variation and anti-metastability design techniques are of growing importance in order to alleviate imperfections of nanoscale CMOS technologies. The paper surveys recent developments of time-to-digital conversion techniques to give a possibly comprehensive picture of major trends and design advancements. Finally, we highlight TDC design challenges for cutting-edge applications such as All-Digital Phase Locked Loops for high data rate wirelesss communication systems operating in the millimeter-wave band.

Characterization of a novel radiation hardened by design (RHD14) bit-cell based on 20-nm FinFET technology using TCAD simulations

Radiation has been a traditional concern in microelectronic devices used in space applications, causing high probability of single event upsets (SEUs). SEUs induced by particle radiation are becoming an increasingly important threat to the reliability of memories. Moreover, recent studies reveals that single event multiple-node upsets (SEMNUs) is the prime effect of radiation in SRAM chips fabricated in nanoscale CMOS technologies. In view of the weaknesses of the existing radiation hardened bit-cell configurations, a highly reliable radiation hardened by design (RHD14) bit-cell is proposed in this paper to address the issues related to SEUs and SEMNUs. Hardness against radiation of the proposed bit-cell is compared with the recently reported radiation hardened bit-cells and popular SRAM bit-cell (6T). Radiation and its effect in the bit-cells under consideration are simulated with the help of 3-D Technology Computer Aided Design (TCAD) and Visual Particle (VP) tools. Radiation hardening capability of RHD14 over the existing and conventional bit-cells is demonstrated focusing on linear energy transfer (LET) threshold and recovery time. It is observed that the proposed radiation hardened cell needs lesser silicon area and performs better in terms of power dissipation. Other performance metrics like read delay, write delay are also evaluated in order to study ensuing trade-off.

Novel qutrit circuit design for multiplexer, De-multiplexer, and decoder

Designing conventional circuits present many challenges, including minimizing internal power dissipation. An approach to overcoming this problem is utilizing quantum technology, which has attracted significant attention as an alternative to Nanoscale CMOS technology. The reduction of energy dissipation makes quantum circuits an up-and-coming emerging technology. Ternary logic can potentially diminish the quantum circuit width, which is currently a limitation in quantum technologies. Using qutrit instead of qubit could play an essential role in the future of quantum computing. First, we propose two approaches for quantum ternary decoder circuit in this context. Then, we propose a quantum ternary multiplexer and quantum ternary demultiplexer to exploit the constructed quantum ternary decoder circuit. Techniques to achieve lower quantum cost are of importance. We considered two types of circuits, one in which the output states are always restored to the initial input states and the other in which the states of the output are irrelevant. We compare the proposed quantum ternary circuits with their existing counterparts and present the improvements. It is possible to realize the proposed designs using macro-level ternary gates that are based on the ion-trap realizable ternary 2-qutrit Muthukrishnan–Stroud and 1-qutrit permutation gates.

High Reliability Soft Error Hardened Latch Design for Nanoscale CMOS Technology using PVT Variation

High Reliability Soft Error Hardened Latch Design for Nanoscale CMOS Technology using PVT Variation

Optimal Optical Receivers in Nanoscale CMOS: A Tutorial

The integration of optical receivers in nanoscale CMOS technologies is challenging due to less intrinsic gain and more noise compared to SiGe BiCMOS technologies. Recent research revealed that low-noise, high-gain, and low-power CMOS optical receivers can be designed by limiting the bandwidth of the front-end followed by equalization techniques that benefit from good switching characteristics offered by CMOS technologies. In this tutorial brief, the operation of decision-feedback equalization, feed-forward equalization, and continuous-time linear equalization is reviewed in the context of high baud-rate 2-PAM and 4-PAM modulation. Recent advances and techniques in 4-PAM optical receivers are reviewed and compared in terms of speed, sensitivity, bandwidth, and efficiency.

BTI-Aware Timing Reliability Improvement of Pulsed Flip-Flops in Nano-Scale CMOS Technology

Pulsed Flip-flops (FFs) are popular elements in the design of high-speed microprocessors. Technology scaling has led to a considerable increase in manufacturing process variation and aging phenomena affecting the reliability of these FFs. In this paper, the timing reliability of pulsed FFs is improved using a transistor-level restructuring technique. In this technique, we modify the pull-down network of pulsed FFs for decreasing the stress time (i.e., the time of being ON) of the pulsed clock transistors. Extensive Monte-Carlo based HSPICE simulations are conducted to show the effectiveness of the proposed restructuring technique under different process variation ratios and lifetime values. The obtained experimental result showed that the lifetime reliability of pulsed FFs is improved by 15% and at the expense of 4% area overhead under 30% process variation ratio and 9 years of operation time.

Lifetime Reliability Improvement of Nano-Scale Digital Circuits Using Dual Threshold Voltage Assignment

In nano-scale CMOS technology, circuit reliability is a growing concern for complicated digital circuits due to manufacturing process variation and aging effects. In this paper, a statistical circuit optimization framework is presented to analyze and improve the lifetime reliability of digital circuits in the presence of process variation and aging degradation. The proposed framework takes advantage of a process variation- and aging-aware gate-level delay degradation model to characterize and evaluate the lifetime reliability of combinational circuits. A metric called Guardband-Aware Reliability (abbreviated as GAR) is proposed for a fair evaluation of the lifetime reliability of combinational circuits considering a guardband and timing yield specified by the designer. Then, using a criticality metric, a set of statistically critical gates is selected for being optimized in the optimization framework. As the improvement procedure, the dual-threshold voltage assignment technique is applied to the identified critical gates to enable the manufactured chip to improve the lifetime reliability in terms of low timing yield loss. Experimental results on ISCAS’85 and ISCAS’89 benchmark circuits show that our proposed framework increases the circuit reliability up to 9.93% for a 6-year lifetime imposing less than 6.9% timing yield loss.

A Comparative Analysis between Standard and mm-Wave Optimized BEOL in a Nanoscale CMOS Technology

This paper presents an extensive comparison of two 28-nm CMOS technologies, i.e., standard and mm-wave-optimized (i.e., thick metals and intermetal oxides) back-end-of-line (BEOL). The proposed comparison is carried out at both component and circuit level by means of a quantitative analysis of the actual performance improvements due to the adoption of a mm-wave-optimized BEOL. To this end, stand-alone transformer performance is first evaluated and then a complete mm-wave macroblock is investigated. A 77-GHz down-converter for frequency modulated continuous wave (FMCW) long-range/medium range (LR/MR) radar applications is exploited as a testbench. For the first time, it is demonstrated that thicker metals and intermetal oxides do not guarantee significant improvements at mm-wave frequencies and a standard (low-cost) BEOL is competitive in comparison with more complex (expensive) ones.

Switched-Capacitor-Assisted Power Gating for Ultra-Low Standby Power in CMOS Digital ICs

This article presents Switched-Capacitor assisted Power Gating (SwCap PG) for reducing the leakage currents of large digital circuits. For the first time, PG switch is biased in the super turn-off and the super turn-on mode during the off-state and the on-state, respectively. A simple switched-capacitor network reconfigures and biases the PG switch in four different possible states with low area and power overhead. During the super turn-off, voltage stress is avoided in the PG switch when the circuit load uses supply voltage equal to the nominal $\text{V}_{\mathbf {DD}}$ in a given technology, and maximum possible leakage current reduction is achieved by the optimal biasing of the gate voltage. The proposed SwCap PG is experimentally validated in the 180nm CMOS technology. Measurement results of CMOS SwCap PG show that leakage current and $\text{R}_{\mathbf {ON}}$ reduce by 186- $226\times $ and 18% respectively, as compared to the conventional PG. An alternate solution for SwCap network using MEMS devices as the switching elements is implemented for additional benefits. Measurement results of MEMS SwCap PG show that leakage current and $\text{R}_{\mathbf {ON}}$ reduce by $172\times $ and 26% respectively, compared to the conventional PG. Finally, the applicability of the SwCap PG in the nano-scale CMOS technologies is addressed.

Soft Error Reliability Evaluation of Nanoscale Logic Circuits in the Presence of Multiple Transient Faults

Radiation-induced single transient faults (STFs) are expected to evolve into multiple transient faults (MTFs) at nanoscale CMOS technology nodes. For this reason, the reliability evaluation of logic circuits in the presence of MTFs is becoming an important aspect of the design process of deep submicron and nanoscale systems. However, an accurate evaluation of the reliability of large-scale and very large-scale circuits is both very complex and time-consuming. Accordingly, this paper presents a novel soft error reliability calculation approach for logic circuits based on a probability distribution model. The correctness or incorrectness of individual logic elements are regarded as random events obeying Bernoulli distribution. Subsequently, logic element conversion-based fault simulation experiments are conducted to analyze the logical masking effects of the circuit when one logic element fails or when two elements fail simultaneously. On this basis, the reliability boundaries of the logic circuits can efficiently be calculated using the proposed probability model and fault simulation results. The proposed solution can obtain an accurate reliability range through single fault and double faults simulations with small sample sizes, and also scales well with the variation of the error rate of the circuit element. To validate the proposed approach, we have calculated the reliability boundaries of ISCAS’85, ISCAS’89, and ITC’99 benchmark circuits. Statistical analysis and experimental results demonstrate that our method is effective and scalable, while also maintaining sufficiently close accuracy.

A Predictive 3-D Source/Drain Resistance Compact Model and the Impact on 7 nm and Scaled FinFETs

Due to the increasing importance and complexity of source/drain parasitic resistance (Rsd) in nanoscale CMOS technology and circuit design, a predictive 3-D structure-aware Rsd compact model is developed and comprehensively validated in respect of 7-nm bulk FinFET TCAD platform. Our TCAD model was calibrated against GlobalFoundries/Samsung 7-nm FinFET technology experimental data and further validated by 2-D Poisson–Schrodinger simulation. Verilog-A coded SPICE Rsd compact model, coupled with proper transport models, indicates that the degradation of saturation current as well as the proportion of Rsd to total device resistance continues to increase from 45% to 49%, and 52% with the scaling of the FinFET from 7 to 5, and 3-nm FinFETs, with errors of less than 4%. TCAD and compact model simulation results both show that the extension and epitaxial contact regions become dominant while metal contact resistivity can be reduced below 6– ${8} \times {10}^{-{9}} \,\, \Omega \cdot \text {cm}^{{2}}$ .

Design of Robust Latch for Multiple-Node Upset (MNU) Mitigation in Nanoscale CMOS Technology

Multiple-node upsets (MNUs) caused by charge sharing effects are dramatically increasing in advanced nanoscale digital latches. Consequently, the robust latches against MNU cases are increasingly important. Although some existing robust latches are designed to recover MNU cases, they incur significant hardware redundancy and more sensitive nodes due to only depending on multiple circuit instances (e.g., C-elements (CEs)). In order to obtain a balance between high tolerance capability and low overheads, in this paper, we propose a novel radiation hardened latch (RHL) based on the polarity of the radiation-induced voltage pulse (positive or negative pulse). The proposed latch is capable of tolerating any possible single node upset (SNU) and MNU cases in all considered nodes while manifesting fewer transistors and sensitive nodes. The timing (transparent and hold) function and reliability are successfully verified by simulation in TSMC 65nm bulk CMOS process. In addition, the results of the cost comparison have illustrated that the proposed RHL latch has a moderate area and power dissipation, but provides significant benefit in terms of both delay and power-delay-area-product (PDAP) among the alternative latches.

Compact ESD Protection Cell for Multi-Band Millimeter-Wave Applications

A compact electrostatic discharge (ESD) protection cell is proposed for multi-band millimeter-wave (MMW) circuits in nanoscale CMOS technology. The proposed ESD protection cell consists of a silicon-controlled rectifier (SCR) and a diode as the main ESD protection devices, and an inductor in this cell is divided into several sections to resonate at multifrequencies. The proposed design has been demonstrated for 28- and 67-GHz applications. The measurement results show that the proposed design exhibits lower loss at the specified frequency bands, higher ESD robustness, and sufficiently small layout area. Therefore, the novel compact ESD protection cell will be better for multi-band MMW applications in CMOS technology.

Information Assurance Through Redundant Design: A Novel TNU Error-Resilient Latch for Harsh Radiation Environment

In nano-scale CMOS technologies, storage cells such as latches are becoming increasingly sensitive to triple-node-upset (TNU) errors caused by harsh radiation effects. In the context of information assurance through redundant design, this article proposes a novel low-cost and TNU on-line self-recoverable latch design which is robust against harsh radiation effects. The latch mainly consists of a series of mutually interlocked 3-input Muller C-elements (CEs) that forms a circular structure. The output of any CE in the latch respectively feeds back to one input of some specified downstream CEs, making the latch completely self-recoverable from any possible TNU, i.e., the latch is completely TNU-resilient. Simulation results demonstrate the complete TNU-resiliency of the proposed latch. In addition, due to the use of fewer transistors and a high-speed path, the proposed latch reduces the delay-power-area product by approximately 91 percent compared with the state-of-the-art TNU hardened latch (TNUHL), which cannot provide a complete TNU-resiliency.

The State of the Art in CMOS VCOs: Mm-Wave VCOs in Advanced CMOS Technology Nodes

There is a growing interest in the realization of highly integrated radar transceivers operating at millimeter-wave (mm-wave) frequencies. In this case, CMOS is the natural technology choice. Modern nanoscale CMOS technologies offer excellent transistor performance with transit frequencies ( f T ) and maximum oscillation frequencies ( f max) exceeding several hundreds of gigahertz. This enables the realization of highly integrated, digitally intensive transceiver systems on chip for mmwave applications, such as 77-GHz automotive radar [1] or wireless data communication systems [2]. Several advanced nanoscale CMOS nodes even surpass the f T and f max values achieved by silicon germanium (SiGe) heterojunction bipolar transistor technologies [3].

A Generic Block-Level Error Confinement Technique for Memory Based on Principal Component Analysis

Nanoscale CMOS technology has encountered severe reliability issues especially in on-chip memory. Conventional word-level error resilience techniques such as Error Correcting Codes (ECC) suffer from high physical overhead and inability to correct increasingly reported multiple bit flip errors. On the other hands, state-of-the-art applications such as image processing and machine learning loosen the requirement on the levels of data protection, which result in dedicated techniques of approximated fault tolerance. In this work, we introduce a novel error protection scheme for memory, based on feature extraction through Principal Component Analysis and the modular-wise technique to segment the data before PCA. The extracted features can be protected by replacing the fault vector with the averaged confinement vectors. This approach confines the errors with either single or multi-bit flips for generic data blocks, whilst achieving significant savings on execution time and memory usage compared to traditional ECC techniques. Experimental results of image processing demonstrate that the proposed technique results in a reconstructed image with PSNR over 30 dB, while robust against both single bit and multiple bit flip errors, with reduced memory storage to just 22.4% compared to the conventional ECC-based technique.