Lifetime Reliability Improvement of Nano-Scale Digital Circuits Using Dual Threshold Voltage Assignment

Mohsen Raji,Reza Mahmoudi,Behnam Ghavami,Saeed Keshavarzi

doi:10.1109/access.2021.3103200

Abstract

In nano-scale CMOS technology, circuit reliability is a growing concern for complicated digital circuits due to manufacturing process variation and aging effects. In this paper, a statistical circuit optimization framework is presented to analyze and improve the lifetime reliability of digital circuits in the presence of process variation and aging degradation. The proposed framework takes advantage of a process variation- and aging-aware gate-level delay degradation model to characterize and evaluate the lifetime reliability of combinational circuits. A metric called Guardband-Aware Reliability (abbreviated as GAR) is proposed for a fair evaluation of the lifetime reliability of combinational circuits considering a guardband and timing yield specified by the designer. Then, using a criticality metric, a set of statistically critical gates is selected for being optimized in the optimization framework. As the improvement procedure, the dual-threshold voltage assignment technique is applied to the identified critical gates to enable the manufactured chip to improve the lifetime reliability in terms of low timing yield loss. Experimental results on ISCAS’85 and ISCAS’89 benchmark circuits show that our proposed framework increases the circuit reliability up to 9.93% for a 6-year lifetime imposing less than 6.9% timing yield loss.

Highlights

Technology scaling allows to fabricate chips with higher complexity and performance, it poses a severe challenge for reliable digital circuit design
Negative Bias Temperature Instability (BTI) occurring in PMOS transistors and Positive BTI affecting NMOS transistors increases the absolute value of threshold voltage (Vth) of transistors and the delay of the circuits increases with the operation time [7]
It is necessary to consider the effects of process variation (PV) and aging ( BTI mechanisms) in the analysis and improvement of lifetime reliability in nano-scale digital circuits

Summary

Introduction

Technology scaling allows to fabricate chips with higher complexity and performance, it poses a severe challenge for reliable digital circuit design. Negative BTI occurring in PMOS transistors and Positive BTI affecting NMOS transistors increases the absolute value of threshold voltage (Vth) of transistors and the delay of the circuits increases with the operation time [7]. It is necessary to consider the effects of PV and aging ( BTI mechanisms) in the analysis and improvement of lifetime reliability in nano-scale digital circuits. Based on the probabilistic delay models, SSTA estimates the probability distribution of the circuit performance under the variation of process parameter in a single timing analysis with a statistical approach. Charge trapping in thin silicon oxide layer is another reason of BTI These phenomena gradually cause increasing threshold voltage (Vth) during lifetime

Methods

Results

Conclusion