Tutorial T6: Robust Design of Nanoscale Circuits in the Presence of Process Variations

Abstract

The lack of process uniformity in the semiconductor manufacturing has caused variability to become the primary cause of concern for nanometer scale CMOS design. The variations are caused by either global effects such as mask imperfections and lens aberration, or local effects such as layout pattern variations. These variations result in a significant amount of spread in the performance as well as leakage of the manufactured circuits. The effect of variations on circuit leakage current is much more pronounced compared to their effect on the delay. The variations can cause up to 30% variations in the circuit delay and up to 20X variations in the leakage current. Due to this, a large number of chips with significantly large leakage have to be discarded, thus resulting in a considerable yield loss. The microelectronics industry is now facing one of the most important and difficult challenges - the loss of predictability in the functional correctness and performance of nanometer scale integrated circuits. For technology to continue to advance along Moore's curve, it has become imperative to develop techniques to both predict and to optimize the performance of ICs in the presence of process variations. The proposed full day tutorial will be a comprehensive look at the state-of-art techniques for (1) accurately predicting the performance and power in the presence of both inter-die and intra-die process variations, accounting for spatial correlations, and (2) optimizing the power and/or performance in the presence of process variations. The tutorial will cover four main topics: 1. Introduction to process variations: sources and their impact 2. Statistical models for gates and interconnect 3. Statistical static timing analysis and total leakage analysis 4. Performance and power optimization in the presence of process variations.