BTI-Aware Timing Reliability Improvement of Pulsed Flip-Flops in Nano-Scale CMOS Technology

Abstract

Pulsed Flip-flops (FFs) are popular elements in the design of high-speed microprocessors. Technology scaling has led to a considerable increase in manufacturing process variation and aging phenomena affecting the reliability of these FFs. In this paper, the timing reliability of pulsed FFs is improved using a transistor-level restructuring technique. In this technique, we modify the pull-down network of pulsed FFs for decreasing the stress time (i.e., the time of being ON) of the pulsed clock transistors. Extensive Monte-Carlo based HSPICE simulations are conducted to show the effectiveness of the proposed restructuring technique under different process variation ratios and lifetime values. The obtained experimental result showed that the lifetime reliability of pulsed FFs is improved by 15% and at the expense of 4% area overhead under 30% process variation ratio and 9 years of operation time.