Performance improvement of embedded low-power microprocessor cores by selective flip flop replacement

Abstract

Performance improvement of an ARM926 microprocessor core by selective replacement of standard master-slave flip flops using low-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> flip flops or a novel type of pulsed flip flop (P-FF) is investigated. Different replacement strategies are proposed that are independent of path and pipeline topologies. These strategies are compared to each other concerning performance improvement and costs. For an existing 90 nm CMOS design a 5% speed improvement on design level is achieved at low area overhead of 1%. An experimental verification of the proposed concept using a loop of critical paths shows 12% speed increase at 500 MHz and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> =1.2 V in a 65 nm CMOS technology.