Impacts of Process Variations and Aging on Lifetime Reliability of Flip-Flops: A Comparative Analysis

Abstract

Aggressive technology scaling has led to significant increase in manufacturing process variations as well as transistors aging effects. In this paper, the impacts of process variations and aging mechanisms on lifetime reliability of flip-flops (FFs) is comparatively investigated. In order to have a fair analysis, a novel criteria called Timing Yield-aware lifetime Reliability (TYR) metric is proposed in which the timing yield determined by the user/designer for the FF is considered as the reference point for its lifetime reliability analysis. Based on TYR, master-salve and pulsed FFs are studied and compared considering main sources of variabilities such as process variations as well as aging effects. Extensive Monte-Carlo based HSPICE simulations are exploited to statistically evaluate and compare the timing reliability of FFs in addition to their power consumption and power-delay-products. The experimental results show that, for a 95% timing yield and under the variation ratio of 15% and 3 years of operation time, the lifetime reliability of pulsed FFs decrease to 63%, while master-slave FFs lifetime reliability degrade to 56%. The lifetime reliability of some master-slave FF (i.e., SDFF) reduce by 40% under the worst condition in the analysis (i.e., variation ratio of 30% and 9 years of operation). However, a FF called cross charge control FF (XCFF) shows the best lifetime reliability among other FFs against both aging and process variations. The proposed metric and methodology can be used as well-defined guidelines for FF topology selection during high reliable circuit design.