A Statistical Gate Sizing Method for Timing Yield and Lifetime Reliability Optimization of Integrated Circuits

Abstract

As CMOS devices become smaller, process and aging variations become a major issue for circuit reliability and yield. In this paper, we propose a new two-phase gate sizing approach in order to improve the reliability of the circuit considering the joint effect of process variation and transistor aging. In the first stage, the initial delay of the circuit is optimized to improve the timing yield of the circuit. Then, in the second stage, we reduce the delay degradation induced by aging and process variations. To this end, two novel concepts called aging probability and delay degradation-aware gate criticality are introduced which enable us to perform gate sizing efficiently using an adaptive multi-objective ranking approach. Experimental results based on ISCAS'85 and EPFL benchmark circuits show that, the proposed method achieves the 95 percent timing yield constraint and the 10 percent timing guard-band as the lifetime reliability constraint at the expense of 13.72 percent area overhead, on average. In comparison with the state-of-the-art methods, the proposed approach imposes lower area overhead with acceptable runtime.