N-type Metal-oxide-semiconductor Research Articles

Anomalous Hot-Carrier-Induced Linear Drain Current Degradation of LDMOS Under Pulse Gate Stress With Different Amplitudes

In this letter, the hot-carrier-induced linear drain current degradations of the n-type lateral double-diffused MOS (LDMOS) transistor under the pulse gate stress with different amplitudes and the worst dc gate stress are experimentally compared. They show that the degradation under the 1.5 V pulse gate stress is less than that under the worst dc gate stress (1.5 V). However, under the 5 V pulse gate stress, the degradation is about two times larger than that under the worst dc gate stress because of the enhanced impact ionization at the pulse falling edge. In this way, the large gate pulse amplitude stress is used for evaluating the hot-carrier-induced lifetime of the LDMOS working with the large gate pulse.

High-Frequency Capacitance–Voltage Characteristics of N-Type Metal–Oxide–Semiconductor Capacitor Based on Strained-Si/SiGe Architecture

An accumulation metal–oxide–semiconductor (MOS) capacitor plays a key role in RF integrated circuits owing to its high linearity and independence of the operation frequency. The high-frequency capacitance–voltage (C–V) characteristics of a strained-Si/SiGe N-type MOS (NMOS) capacitor were studied to explain a measured behavior in which a “plateau” in the accumulation region was observed. By physically deriving the model of the NMOS capacitor, it was found that this plateau is substrate-doping-dependent and can also be strongly affected by the strained-Si layer thickness. The results from the model were compared with the experimental results and found to be in excellent agreement, indicating the validity of the model. The proposed model can provide valuable reference to the strained-Si device design and has been implemented in the software for extracting the parameter of a strained-Si MOSFET.

Hot hole-induced device degradation by drain junction reverse current

In this paper, device degradation mechanisms by drain junction reverse current in the off-state were studied, using n-type metal–oxide–semiconductor field-effect transistor (N-MOSFET), which is used as the high-voltage core circuit of flash memory chip. Components of drain leakage currents in the off-state are gate-induced drain-leakage (GIDL) and drain junction reverse currents. Device degradation phenomenon and mechanism by GIDL in the MOSFETs have been well known, but those by drain junction reverse current have not. A variety of measurement conditions for separating drain junction reverse current from total drain current in the off-state were suggested, and hole injection phenomenon into the gate was investigated through the modified capacitive-voltage method. In addition, we investigated the location of electron–hole generation between GIDL and drain junction reverse current through the lateral profile of trapped hole extracted from charge pumping method.

Optimization of Dislocation Edge Stress Effects for Si N-Type Metal–Oxide–Semiconductor Field-Effect Transistors

The comprehensive investigation on the effect of dislocation edge stress for Si N-type metal–oxide–semiconductor field-effect transistors (N-MOSFETs) is presented in this work by the experimental measurement and proposed simulation model. The accurate stress measurement in Si oxide dimension (OD) region with and without dislocation edge stress treatment is extracted by atomic force microscope (AFM)–Raman technique with the nanometer level space resolution. Less compressive stress in Si OD region on the real transistor with dislocation edge stress treatment is observed successfully and has its corresponding higher electron carrier mobility, agreed with the strained Si theory. Main reasons for the less compressive stress in the device with dislocation edge stress treatment are the more stress relaxation of the shallow trench insulator (STI) intrinsic compressive stress in modern CMOS process and one layer Si atom missing near the source and drain region along the dislocation line. The measured stress from AFM–Raman spectra experimentally, the simulated stress from proposed finite element method, and its corresponding electrical characteristics agrees well with each other in this work. After the comprehensive understanding and calibrated model for the dislocation edge stress, the relationship between channel stress and dislocation edge shapes, including the angle and length of dislocation lines, is simulated and investigated clearly. It can be found that longer dislocation line and smaller dislocation angle can relax the intrinsic STI compressive stress more and should have the better electron carrier mobility and device performance for N-MOSFETs.

Characterization of Oxide Traps in 28 nm n-Type Metal–Oxide–Semiconductor Field-Effect Transistors with Different Uniaxial Tensile Stresses Utilizing Random Telegraph Noise

In this study, the effect of uniaxial tensile on the SiO2/Si interface of the 28 nm n-type metal–oxide–semiconductor field-effect transistors (nMOSFETs) has been investigated. nMOSFETs were fabricated with different thicknesses of the stress-memorization technique (SMT) films to further increase channel stress because the SMT films can provide a higher uniaxial tensile to the channel. Trap behaviors such as activation energy and depth were characterized on the basis of drain current random telegraph noise (RTN). By RTN analyses, we found that the trap energy level is closer to the channel conduction band as the tensile strain in the channel increases higher, resulting in the trap being located close to the SiO2/Si interface.

Characterization of silicon dioxide films on 4H-SiC (0001) Si, (1-100) M, and (11-20) A faces by cathodoluminescence spectroscopy

We prepared SiO2 films with channel mobilities (CMs) of 35, 105, and 112 cm2/Vs on 4H-SiC (0001) Si, (1-100) M, and (11-20) A faces by post-oxidation annealing (POA) in NO ambient and measured the cathodoluminescence (CL) spectra. For an acceleration voltage of 5 kV, the CL peak assigned to oxygen vacancy centers (OVCs) weakens by POA, whereas the CL peak related to Si-N bonding structures intensifies with increasing CM. This suggests that OVCs in the SiO2/SiC interface are terminated by N. We show that NO ambient POA increases the CM more effectively than that by N2O ambient. CL spectroscopy provides us with extensive information on OVCs, non-bridging oxidation hole centers, and dangling bonds in the SiO2/SiC interface on 4H-SiC substrates and on the CM in n-type MOS capacitors.

Generation and Shaping of Soliton-Like Pulses along Resonant Tunneling Diodes NMOS Varactors Lattice

The characteristics of N-type accumulation-mode MOS (NMOS) varactors line periodically loaded with resonant tunneling diodes (RTDs) are used for soliton-like pulses generation and shaping. The problem of wide pulse breaking up into multiple pulses rather than a single is solved. Applying perturbative analysis, we show that the dynamics of the nonlinear transmission line (NLTL) is reduced to expanded Korteweg-de Vries (KdV) equation. Moreover, numerical integration of nonlinear differential and difference equations that result from the mathematical analysis of the line is discussed. As results, NLTL can simultaneously sharpen both leading and trailing of pulse edges and one could obtain a rising and sharpening step pulse.

Ohmic contact on n-type Ge using Yb-germanide

Poor ohmic contact by Fermi-level pinning to valence band (EV) edge is one of the major challenges for germanium (Ge) n-type metal–oxide–semiconductor field-effect transistor (nMOSFET). Using low work-function rare-earth ytterbium (Yb), good ohmic contact on n-type Ge with alleviated Fermi-level pinning was demonstrated. Such ohmic behavior depends strongly on the germanide formation condition, where much degraded ohmic contact at 600 °C rapid thermal annealing is due to the lower Yb/Ge composition found by energy-dispersive x-ray spectroscopy. The ohmic behavior of Yb-germanide/n-type-Ge has high potential for future high-performance Ge nMOSFET application.

Photoenergy Conversion in p-Type Cu2ZnSnS4 Nanorods and n-Type Metal Oxide Composites

Single-crystalline Cu2ZnSnS4 (CZTS) nanorods with a kesterite crystal phase were synthesized using a facile solvothermal reaction. Thin-film electrodes for p-type CZTS nanorods and n-type metal oxide semiconductor composites were fabricated on mesoporous n-type metal oxide electrodes by introducing the electrodes into a solvothermal condition. The composites exhibited high photocurrent and strong photocatalytic oxidative activity for the decomposition of organic compounds.

Electrical and Reliability Characteristics of HfLaTiO-Gated Metal–Oxide–Semiconductor Capacitors With Various Ti Concentrations

Electrical and reliability characteristics of metal-oxide-semiconductor (MOS) capacitors with various-Ti-concentration-doped HfLaTiO/interfacial layer (IL)/P-Si(100) stacked structures are presented. Charge carrier generation/trapping and the related mechanisms of a thin HfLaTiO/IL stack in n-type MOS capacitors have been investigated under constant gate voltage stress. The mechanisms related to larger positive charge generation in the HfLaTiO gate dielectric bulk can be attributed to Ti-doped HfLaTiO dielectric. This is confirmed from the density of stress-induced oxide trapped charges. Moreover, more positive charges are induced in the HfLaTiO dielectric with increasing postdeposition annealing temperature. By developing proper Ti concentration in HfLaTiO dielectrics, the enhanced equivalent oxide thickness (EOT = ~ 0.5 nm) and the interface trap density ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it</sub> ) were demonstrated. Furthermore, the Ti-doped HfLaTiO dielectric is helpful for enhanced <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> -value of the HfLaTiO film (lower EOT), but the optical bandgap properties could be degraded. Energy band diagram of MOS capacitor with an HfLaTiO dielectric was achieved by the measurement of the effective work function of Ta metal gate deposited on HfLaTiO dielectric, the optical bandgaps of HfLaTiO dielectric, and Schottky barrier height (Φ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</i> ) at the Ta/HfLaTiO interface.

Sub-Bandgap Light-Induced Carrier Generation at Room Temperature in Silicon Carbide MOS Capacitors

Carrier generation characteristics in n-type substrate SiC MOS capacitors induced by sub-bandgap energy light are reported. The generation rate is high enough to create an inversion layer in ~20 minutes with monochromatic light (front side illumination) of energy 2.1 eV in 4H-SiC for electric fields smaller than 1 MV/cm. Generation and recovery results strongly indicate involvement of a metastable defect whose efficiency as a generation center increases under hole-rich and decreases under electron-rich conditions. The generation dependence on bias history and light energy shows the defect to have properties consistent with the metastable silicon vacancy / carbon vacancy-antisite complex (VSi / Vc - CSi).

Fabrication and Electrical Properties of Thermally Oxidized p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors on 4H-SiC C-Face

We characterized the SiO2/SiC interface by capacitance–voltage (C–V) measurement in order to obtain p-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) on the 4H-SiC(0001̄) C-face. Wet gate oxidation was preferable for both n- and p-type MOS capacitors, but p-type MOS interface properties were inferior to those of n-type MOS capacitors. The cause of the large flat-band shift for the p-type sample was discussed on the basis of C–V measurements by the light illumination technique. We also investigated the influence of the high-temperature annealing process after gate oxidation on the MOS interface properties. The p-type MOS interface was more sensitive to the annealing process than the n-type MOS interface. We fabricated 4H-SiC C-face p-channel MOSFETs by wet gate oxidation and low-temperature postdeposition annealing in He–H2 ambient. The normal FET operation was accomplished on the 4H-SiC C-face for the first time. Those devices, however, indicated low channel mobility and large threshold voltage.

The electrical and structural properties of HfO2/SrTiO3 stacked gate dielectric with TiN metal gate electrode

The electrical and structural properties of HfO2/SrTiO3 composite gate dielectric are discussed for achieving higher dielectric constant to reduce equivalent oxide thickness (EOT) as well as to tune threshold voltage (VTH) in n-type metal oxide semiconductor transistor. Compared to atomic layer deposited (ALD) HfO2 alone, adding 0.5–1.0nm sputtered SrTiO3 layer into ALD HfO2 gate dielectric attains EOT scaling down to about 0.6nm, ~700mV negative VTH shift, comparable gate leakage current at both fixed 1V and VTH+0.8V overdrive conditions and electron mobility with of 137cm2/V.s at 0.6nm EOT. This is attributed to the significant modification of the interfacial layer (IL), resulting from Sr diffusion into sub-SiOx IL during subsequent anneal in gate-first transistor processes. It leads to SrOx IL formation between high-k gate insulator layer and Si substrate, where its dielectric constant is about three times higher than that of SiOx IL.

Characterization of silicon dioxide films on 4H-SiC Si (0001) face by cathodoluminescence spectroscopy and x-ray photoelectron spectroscopy

We measured cathodoluminescence (CL) spectra of SiO2 films grown on 4H-SiC wafers and found that for an acceleration voltage of 5 kV, CL peaks at 460 and 490 nm, assigned to oxygen vacancy centers (OVCs), become weak by post-oxidation annealing in N2O ambient at 1300 °C whereas the CL peak around 580 nm, related to Si-N bonding structures, becomes intense. Furthermore, the peak assigned to N-Si3 configurations in x-ray photoelectron spectroscopy (XPS) spectra was observed in the SiO2/SiC interface in only samples annealed in N2O ambient. These results suggest that the interface trap densities decrease and the channel mobility in n-type MOS capacitors increases by the termination of dangling bonds by the N atom in the SiO2/SiC interface. CL spectroscopy and XPS provide us with extensive information on OVCs and dangling bonds in the SiO2/SiC interface on the 4H-SiC substrate.

Comparison of Electrical Behavior of GaN-Based MOS Structures Obtained by Different PECVD Process

MOS SiO2/GaN structures were fabricated with different surface preparation and different PECVD processes for the dielectric thin film deposition (ECR-PECVD and ICP-PECVD in continuous and pulsed modes). On the basis of C-V curves, the surface preparation steps, involving chemical etching with BOE, UV-Ozone oxidation and oxygen plasma oxidation, were compared in terms of resulting effective charge and interface trap density. A good SiO2/GaN interface quality was achieved for N-type MOS capacitances obtained both with continuousICPPECVD and ECR-PECVD deposition of the SiO2 dielectric. However, the interface quality is greatly reduced for MOS capacitors fabricated on P-type GaN.

Integrated SRAM compiler with clamping diode to reduce leakage and dynamic power in nano-CMOS process

An integrated static random access memory (SRAM) compiler is proposed to reduce both leakage and dynamic power at circuit and architectural level. Based on source biasing scheme, an extra clamping diode in parallel with a pull-down n-type metal-oxide semiconductor transistor is inserted between the ground and source line of a SRAM cell to achieve reduction in the leakage current as well as data retention capability. Bit line charging/discharging current is greatly decreased by introducing extra Z decoding circuits and thus reducing dynamic power significantly. Test chips with 11 embedded SRAMs have been fabricated in UMC 55 nm complementary metal-oxide semiconductor process and the measurement results have proved the effectiveness of the proposed technique.

Enhanced Radiation-Induced Narrow Channel Effects in Commercial &lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;${\hbox {0.18}}~\mu$&lt;/tex&gt; &lt;/formula&gt;m Bulk Technology

Total ionizing dose effects are investigated in input/output transistors that are fabricated by using a commercial 0.18 μm bulk process. An enhanced radiation-induced narrow channel effect is demonstrated in N-type metal-oxide semiconductor (NMOS) and P-type metal-oxide semiconductor (PMOS) transistors, leading to a significant threshold voltage shift which may compromise circuit operations. Calculations using a code dedicated to radiation-induced charge trapping in oxides show that the radiation-induced positive charge trapping in trench oxides leads to the modifications of the electrical characteristics experimentally evidenced. Radiation hardening issues are finally discussed as a function of the device geometry and design.

Dual Metal/High-kGate-Last Complementary Metal–Oxide–Semiconductor Field-Effect Transistor with SiBN Film and Characteristic Behavior In Sub-1-nm Equivalent Oxide Thickness

For the first time, dual metal/high-k gate-last complementary metal–oxide–semiconductor field-effect transistors (CMOSFETs) with low-dielectric-constant-material offset spacers and several gate oxide thicknesses were fabricated to improve CMOSFETs characteristics. Improvements of 23 aF/µm in parasitic capacitances were confirmed with a low-dielectric-constant material, and drive current improvements were also achieved with a thin gate oxide. The drive currents at 100 nA/µm off leakages in n-type metal–oxide–semiconductor (NMOS) were improved from 830 to 950 µA/µm and that in p-type metal–oxide–semiconductor (PMOS) were from 405 to 450 µA/µm with a reduction in gate oxide thickness. The thin gate oxide in PMOS was thinner than that in NMOS and the gate leakage was increased. However the gate leakage did not affect the off leakage below a gate length of about 44 nm. On the basis of this result, in these gate-last CMOSFETs, it is concluded that the transistors have potential for further reduction of the equivalent oxide thickness without an increase in off leakages at short gate lengths for high off leakage CMOSFETs. For low off leakage CMOSFETs, the optimization of wet process condition is needed to prevent the reduction of the 2 nm HfO2 thickness in PMOS during a wet process.

Dual Metal/High-k Gate-Last Complementary Metal–Oxide–Semiconductor Field-Effect Transistor with SiBN Film and Characteristic Behavior In Sub-1-nm Equivalent Oxide Thickness

For the first time, dual metal/high-k gate-last complementary metal–oxide–semiconductor field-effect transistors (CMOSFETs) with low-dielectric-constant-material offset spacers and several gate oxide thicknesses were fabricated to improve CMOSFETs characteristics. Improvements of 23 aF/µm in parasitic capacitances were confirmed with a low-dielectric-constant material, and drive current improvements were also achieved with a thin gate oxide. The drive currents at 100 nA/µm off leakages in n-type metal–oxide–semiconductor (NMOS) were improved from 830 to 950 µA/µm and that in p-type metal–oxide–semiconductor (PMOS) were from 405 to 450 µA/µm with a reduction in gate oxide thickness. The thin gate oxide in PMOS was thinner than that in NMOS and the gate leakage was increased. However the gate leakage did not affect the off leakage below a gate length of about 44 nm. On the basis of this result, in these gate-last CMOSFETs, it is concluded that the transistors have potential for further reduction of the equivalent oxide thickness without an increase in off leakages at short gate lengths for high off leakage CMOSFETs. For low off leakage CMOSFETs, the optimization of wet process condition is needed to prevent the reduction of the 2 nm HfO2 thickness in PMOS during a wet process.

High fluence 1.8 MeV proton irradiation effects on n-type MOS capacitors

MOS capacitors with 7 nm SiO 2 dielectrics and n-doped Si substrate were irradiated by 1.8 MeV protons with fluences ranging from 10 12 to 5 × 10 13 cm −2 which correspond to the typical LHC fluence range. No significant increase in gate oxide leakage current was detected. A decrease of the capacitance was observed in the accumulation regime. This effect is explained by an increase of the substrate resistivity caused by displacement damage.