Integrated SRAM compiler with clamping diode to reduce leakage and dynamic power in nano-CMOS process

Abstract

An integrated static random access memory (SRAM) compiler is proposed to reduce both leakage and dynamic power at circuit and architectural level. Based on source biasing scheme, an extra clamping diode in parallel with a pull-down n-type metal-oxide semiconductor transistor is inserted between the ground and source line of a SRAM cell to achieve reduction in the leakage current as well as data retention capability. Bit line charging/discharging current is greatly decreased by introducing extra Z decoding circuits and thus reducing dynamic power significantly. Test chips with 11 embedded SRAMs have been fabricated in UMC 55 nm complementary metal-oxide semiconductor process and the measurement results have proved the effectiveness of the proposed technique.