N-type Metal-oxide-semiconductor Research Articles

Revealing the Performance-Limiting Factors in α-SnWO4 Photoanodes for Solar Water Splitting

α-SnWO4 is an n-type metal oxide semiconductor that has recently attracted attention as a top absorber material in a D4-tandem device for highly efficient solar water splitting due to the combination of an ideal bandgap (∼1.9 eV) and a relatively negative photocurrent onset potential (∼0 V vs RHE). However, up to now, α-SnWO4 photoanodes have not shown high photoconversion efficiencies for reasons that have not yet been fully elucidated. In this work, phase-pure α-SnWO4 films are successfully prepared by pulsed laser deposition. The favorable band alignment is confirmed, and key carrier transport properties, such as charge carrier mobility, lifetime, and diffusion length are reported for the first time. In addition, a hole-conducting NiOx layer is introduced to protect the surface of the α-SnWO4 films from oxidation. The NiOx layer is found to increase the photocurrent for sulfite oxidation by a factor of ∼100, setting a new benchmark for the photocurrent and quantum efficiency of α-SnWO4. These results p...

Growth and characterization of nitrogen-phosphorus hybrid passivated gate oxide film on N-type 4H-SiC epilayer

A novel nitrogen-phosphorus (N&P) hybrid passivation technique by NO-containing dry oxidation of phosphorus-implanted 4H-SiC epilayer has been proposed to grow high-property gate oxide film. For demonstration and contrast, n-type 4H-SiC MOS capacitors with N&P hybrid and only N passivation have been fabricated and tested. The results from Secondary Ion Mass Spectroscopy (SIMS) reveal that about 60% of the implanted phosphorus atoms remain in the SiO2 film after sacrificial oxidation of the implantation layer. And the distribution of phosphorus is approximately uniform throughout the grown SiO2 film with a concentration about 4 × 1019 cm−3, avoiding the SiO2 film converting to phosphosilicate glass (PSG). I-V and X-ray Photoelectron Spectroscopy (XPS) data show that the grown SiO2 film with the appropriate phosphorus passivation can effectively improve the quality of oxide film, leading the gate oxide bandgap and integrity improved and reducing the leakage current above two orders of magnitude. The bias stress measurements with ultraviolet light (UVL) irradiation also show that the N&P hybrid passivation treatment can completely restrain the near-interface electron traps (NIETs) in 4H-SiC MOS devices, indicating that incorporation an appropriate amount of phosphorus atoms in the grown SiO2 film also can make the electron trap density reduced effectively.

Total ionizing dose and single event effects of 1 Mb HfO2-based resistive-random-access memory

Experiments of total ionizing dose (TID) using a Cobalt-60 source and single event effects (SEE) using pulsed laser and heavy ion were conducted to investigate the radiation effects in 1 Mb HfO2-based resistive-random-access memory (RRAM) with 1T1R (1 access transistor in series with 1 RRAM) storage cell structure. TID-induced leakage current in the access transistors on the same bit-lines caused a read decision failure and the bit errors observed. The failure threshold for the leakage current of access transistor was about 3.4 nA by HSpice simulation, which was also verified by the transfer characteristics of the access N-type Metal-Oxide-Semiconductor (NMOS) transistor in 1T1R cell before and after radiation. The RRAM array was immune to single event upsets (SEU) regardless of the pulsed laser and heavy ion used. The single event latchup (SEL) in row decoder circuits was found to trigger burst of errors, whose physical mapping was analyzed. These analyses and finds are useful for developing radiation-hard RRAM aimed at space applications.

A CMOS Follower-Type Voltage Regulator With a Distributed-Element Fractional-Order Control

This paper presents an application of a fractional-order control in an on-chip follower-type 1.8 V/100 mA voltage regulator to achieve a good stability with any load capacitance. The controller approximates an integrator with the fractional order of 0.5, whose phase lag is not more than 45°. The fractional order is set by the fractional-order impedance of the resistive p-type MOS capacitor (R-PMOScap). With an n-type MOS source follower stage adding the phase lag of at most 90°, the remaining phase margin is always at least 45°. The R-PMOScap is a novel integrated distributed-element RC network, realized as a resistive polysilicon strip on a gate oxide, and is compatible with an analog CMOS process. The voltage regulator has been manufactured in a 350-nm CMOS process and occupies a small chip area of 0.038 mm2. It operates in a harsh automotive environment with a temperature from −50 °C to 200 °C and shows a tight DC regulation, while being stable over the full range of the load current (from 0 to 100 mA) and with any load capacitance (allowing to use none or any external capacitor).

Low-temperature sol-gel ZrHfO2-PMMA hybrid dielectric thin-films for metal oxide TFTs

In this work, we developed a novel inorganic-organic hybrid gate dielectric by combining zirconium and hafnium components to form zirconium hafnium oxide strongly linked with polymethyl methacrylate (ZrHfO2-PMMA) and deposited at low temperature (200 °C) by sol-gel method. The obtained 108 nm thick, high-quality hybrid gate dielectric showed an exceptionally low surface roughness (0.9-nm), a low leakage current density (7.7 × 10−6 A/cm2) and reasonable dielectric properties such as gate capacitance along with dielectric constant (77 nF/cm2 & 9.4 @1 kHz) respectively. To examine the ZrHfO2-PMMA hybrid dielectric electrical properties we constructed thin-film transistors (TFTs) with room temperature r.f sputtered n-type metal oxide semiconductors, a-IGZO and ZnO, as active channels. The bottom gate fabricated a-IGZO TFTs driving at as low as below 6 V, with extracted field effect mobility of 2.45 cm2/V. s, a low threshold voltage of 1.2 V with large ON/OFF current ratio 107 respectively. On the other hand, for comparison we employed ZnO TFTs by applying same hybrid dielectric system, the obtained parameters of bottom gate ZnO TFTs were good field effect saturation mobility of 12.8 cm2/V. s, threshold voltage of 1.8 V and ON/OFF current ratio of 103.

An Improved Hot-Carrier Lifetime Evaluation Method for the n-Type LDMOS With Hot-Hole Injection

The hot-carrier lifetime evaluation method of a 90-V-level n-type lateral double-diffused MOS (LDMOS) is investigated in this brief. Our charge pumping experiments demonstrate that the on-resistance degradation of the device is induced by the combination effect of the hot-hole injection at field oxide region and the interface state generation at field oxide and accumulation regions. Thereby, the hot-carrier lifetime of the device was evaluated by the comprehensive model proposed by Moens, which considers the effects of both hot-hole injection and the interface state generation. However, our experiments found that multiple lifetimes were obtained based on the model proposed by Moens and some lifetimes have the risk of overestimation. To solve the problem, an improved hot-carrier lifetime evaluation method based on a novel semiempirical model is proposed. Further experiments and analyses illustrate that the proposed hot-carrier lifetime evaluation method can provide a definite lifetime that has no risk of overestimation for the investigated LDMOS and has improved the lifetime prediction precision compare to the method based on Hu’s model.

(Invited) New p-Type Oxide Semiconductor with High Hole Mobility over 7 cm2/Vs Formed By Solution Process

We report new p-type metal oxide semiconductor thin-film transistor with high field-effect hole mobility fabricated in solution process in this work. Metal oxide semiconductors have long attracted large attention as large-area electronic devices by virtue of high electrical and optical performances such as transparency, large electron mobility, good uniformity and low-temperature processability since the pioneering work of Prof. Hosono group in 2004, and their mass production has now been successfully realized in the active matrix backplane of flat-panel or flexible display. Few p-type metal oxide semiconductors with high performance, however, have been reported compared with n-type metal oxide semiconductors such as InGaZnO, InZnSnO, etc. This is mostly ascribed as the localization of valence band maximum which mainly consists of oxygen p orbitals. To enhance the dispersion of valence band, it has been theoretically proposed that the filled diffuse metal d or s orbital to hybridize with oxygen 2p orbital can be utilized and indeed it was experimentally demonstrated that Sn 5s orbital and Cu 3d orbital played such a role in SnO and CuO, respectively. But, SnO phase is very vulnerable to disproportion reaction to metallic Sn and SnO2 which behaves as an n-type semiconductor so that the process window to realize it in electron devices was very narrow and the electrical performance in the devices such as thin-film transistor was very limited, e.g low on/off ratio. Inspired by the theoretical work of high throughput materials screening performed by the first principles calculation, we fabricated the alkali metal doped SnO thin-film with solution process and low-temperature annealing less than 400 oC. We found that the oxidation state of Sn in thin-films changed from +4 state (SnO2 phase) to +2 state (SnO phase) depending on the content of alkali metal ions from x-ray photoelectron spectroscopy (XPS). Furthermore, Hall-effect measurement indicated the type conversion of the majority carrier from n-type to p-type as the content of alkali metal ion increases, in consistence with XPS results. The high hall mobility of 51 cm2/Vs was obtained at the optimal alkali-metal ion doped SnO thin film and we successfully fabricated thin-film transistors with alkali-metal ion doped SnO with a field-effect hole mobility over 7 cm2/Vs. We hope that this work will contribute to open a new era for transparent large area electronics based on oxide semiconductors with high functionalities such as complementary logic circuit.

Determination of Phonon Deformation Potentials in Carbon-Doped Silicon

Carbon-doped silicon (Si:C) is used as a stressor to the channel of n-type metal oxide semiconductor field-effect-transistor (MOSFET). In this study, we determined phonon deformation potentials (p and q) of Si:C to realize evaluation of anisotropic biaxial strain by using water-immersion Raman spectroscopy. Raman peak shift in longitudinal and transverse optical (LO and TO) phonon modes were measured by water-immersion Raman spectroscopy. Furthermore, in-plane and out-of-plane strain were measured by X-ray diffraction (XRD). Based on the Raman shift and the in-plane strain, p and q in each sample were derived. As a result, it took a different value from pure-Si, and the PDPs tended to increase as the C concentration increased.

Comparative study on slow-state near interface hole traps in NO and Ar annealed N-type 4H-SiC MOS capacitors by ultraviolet light

The characteristics of near interface charge trapping and releasing on n-type 4H-SiC MOS capacitors with NO and Ar passivation have been systematically investigated through time-dependent bias stress with ultraviolet light irradiation. Flat band voltage instability of the Ar annealed samples mainly results from electrons directly tunneling in and out of the near interface electron traps. However, hole trapping by the near interface hole traps (NIHTs) also need to be concerned for the NO annealed samples. It is found that part of the trapped holes cannot be easily released from the slow-state NIHTs, which may act as the positive fixed charge and induce the unrecoverable negative shift of threshold voltage. The results from XPS show that after the NO annealing, some of the intermediate oxidation states are converted to the strong Si≡N and Si–Ox–Ny bonds located in the transition layer, which may act as NIHTs and even suppress hydrofluoric acid etching. Thus, it is important to optimize nitrogen treatment in order to reduce the density of NIHTs induced in the 4H-SiC MOS devices.

NMOS only Schmitt trigger circuit for NBTI resilient CMOS circuits

A novel N-type MOS (NMOS) only Schmitt trigger with voltage booster (NST-VB) circuit is presented. The proposed NST-VB circuit uses NMOS transistors in both pull-up and pull-down networks to reduce the effect of negative bias temperature instability (NBTI) on the circuit. The proposed circuit is less affected by both inter-die and intra-die process variations in consequence of NMOS only structure. Owing to NBTI, the increase in delay for the proposed NST-VB circuit is only 0.47% as compared with 7.2% for conventional Schmitt trigger after the stress time of three years. For the viability of the proposed circuit figure of merit (FOM) is used as a performance metric and it is found that the proposed circuit has 15.35 × and 3.53 × improved FOM as compared with the conventional Schmitt trigger and NMOS inverter, respectively.

A Simple Transistors Width Adjustment Method on CMOS Transmission Gate Switch to Reduce Hold Error of S/H Circuit

Sample and Hold (S/H) circuit is one of the most important circuits in analog and mixed signal integrated circuit. This circuit is the main block of many applications, such as switched capacitor circuit, analog to digital converter (ADC), etc. The majority of S/H circuits are implemented using MOS technology because the high input impedance of MOS devices performs excellent holding functions. Ideal characteristics of the S/H circuit are low hold error, low On-resistance and constant On-resistance in all voltage levels. There are some techniques to reduce the hold error and achieve low On-resistance. However, these techniques need additional compensation circuit. For this reason, a simple transistors width adjustment method on CMOS transmission gate (TG) switch to reduce hold error of S/H circuit without additional circuit that can be implemented in the actual design process is proposed in this paper. The basic idea of the proposed method is balancing hold error caused by N-type and P-type MOS transistor in CMOS switch that is used in S/H circuit. The performance of the proposed method is evaluated using HSPICE with 0.6 µm CMOS standard process. As a result, using 1.5 V constant input in the PMOS transistor width W P range of 3 to 35 µm the average W N / W P ratio given by this proposed method is 0.928 with the average absolute hold error is 0.427 mV and maximum absolute hold error is 0.8 mV.

Study on NO Passivation on the Near Interface Electron and Hole Traps of n-Type 4H-SiC MOS Capacitors by Ultraviolet Light

The characteristics of near interface electron and hole traps in n-type 4H-SiC MOS capacitors with and without nitric oxide (NO) passivation have been systematically investigated. The hysteresis of the bidirectional capacitance-voltage (C-V) and the shift of flat band voltage (Vfb) caused by bias stress (BS) with and without ultraviolet light (UVL) irradiation are used for studying the influence of near interface electron traps (NIETs) and near interface hole traps (NIHTs). Compared with Ar annealed process, NO passivation can effectively reduce the density of NIETs, but induce excess NIHTs in the SiC MOS devices. What’s worse is that part of the trapped hole cannot be released easily from the NIHTs in the NO annealed sample, which may act as the positive fixed charge and induce the negative shift of threshold voltage.

Correlation between Field Effect Mobility and Accumulation Conductance at 4H-SiC MOS Interface with Barium

A correlation between field effect mobility and an accumulation conductance has been investigated at 4H-SiC MOS interface with barium. 4H-SiC n-channel MOSFETs and n-type MOS capacitors were fabricated with a barium-introduced SiO2 and a conventional dry SiO2. The field effect mobility was enhanced by introducing the barium-introduced SiO2. It is found that there is a linear correlation between the mobility and the accumulation conductance. The MOS interface of the barium-introduced SiO2 had a lower interface state density of 2×1011 cm-2eV-1 than that of the conventional dry SiO2.

3D-Nanorod Fenton-like CuO/TiO2 Photocatalyst By Electrodeposition in AAO Template for Dye Degradation

Recently, nanostructures such as nanorods and nanowires have drawn much interest because of their unique electronic and optical properties. Anodic aluminum oxide (AAO) method is a promising template-assisted technique which ensures high quality and repeatability for fabrication. Morphology of periodical nanoscale pores in AAO templates has been studied in relation with anodizing process for a few decades. The AAO templates are well prepared by a two-step anodization process method in 0.3 M oxalic acid solution at 10 °C and anodizing voltage 40 V. After first-step anodization, AAO layer was etched out in 5 wt.% phosphoric acid and 2.24 wt.% chromic acid at 60 °C for 1 HR. After barrier thinning, the AAO template was immersed into a 5 wt.% phosphoric acid solution at room temperature for 45 minutes. The pore length increases with electrochemical etching time, while the pore size and interpore distance depend on the applied potential. In our work, the AAO template is 45 nm in diameter and the interpore distance and pore length are 100 nm and 1 μm, respectively. In case that the Al2O3 barrier layer is too thick for the electrodeposition, barrier thinning proceeds by limited current is a necessary process to lower the working voltage and to create the nucleation site for the growth of Cu. The Cu/Cu2O composite nanorods are synthesized from aqueous solution prepared from 0.7 M of CuSO4 dissolved in DI water, with applied pulse potential -1.5 V at room temperature. The nanorods were annealed at 400 °C and resulted in the formation of CuO. After that, TiO2 thin film was deposited on the top followed by annealing at 550 °C to form anatase. Etching out the AAO template, we can obtain CuO nanorod arrays standing on TiO2 thin film nanostructure for application in water treatment. Besides, it can also be transferred on other flexible substrate or on the surface of the item promoting self-cleaning property. CuO is a great Fenton-like photocatalyst which is active with H2O2 and produces free radicals reacting with the dye or pollutants. TiO2 is stable in water and possesses good photocatalytic property in anatase phase. CuO is a narrow bandgap p-type metal oxide semiconductor which provides electrons and holes and absorbs infrared light, while TiO2 is a n-type metal oxide semiconductor which absorbs UV light and has high transparency in sunlight. We combine two metal oxide to form heterojunction with AAO and electrodeposition method. When the infrared light is absorbed by CuO nanorods exciting electron and holes, the electrons shift to TiO2 and the holes stay in CuO. These electron-hole pairs can react with H2O2 producing free radicals and start dye degradation. Furthermore, CuO nanorods immobilized on TiO2 film nanostructure can also be applied as gas sensors or photodetectors and for water splitting.

Does the low optical band gap of yellow Bi3YO6 guarantee the photocatalytical activity under visible light illumination?

Bi3YO6, which is known as an ionic conductor, was tested here as an electrode and photoanode in contact with aqueous electrolytes. Bi3YO6 was deposited onto the Pt substrate and the such prepared electrode was polarized in various aqueous electrolytes. The optical energy band gap of the material equal to 1.89 eV was determined using the Kubelka-Munk function resulting from the UV-Vis spectrum (allowed indirect transition) and also was calculated using the semi-empirical PM7 method (3.38 eV of HOMO-LUMO energy gap). Despite the yellow color of Bi3YO6, the tested material exhibits photoelectroactivity only in the UV range of electromagnetic radiation. The anodic photocurrent characteristic for n-type metal oxide semiconductors was recorded. The electrode exhibits diffusion-controlled cathodic activity while polarized in chloride-free aqueous electrolytes.

Wide tuning range low phase noise VCO for V‐band application

In this study, millimetre wave (MMW) voltage controlled oscillator (VCO) is designed using 130 nm complementary metal–oxide–semiconductor single poly eight metals (1P8M) technology. Under 0.8 V supply, VCO can be tuned from 46 to 61.2 GHz, i.e. 28% frequency tuning range (FTR) is achieved. For the highest oscillation frequency, phase noise at 10 MHz offset frequency is −117.3 dBc/Hz, while the power dissipation is 9.39 mW. The FTR is improved by adopting multiband scheme using transformer tuned technique. Improvement in phase noise is done with a P-type metal–oxide–semiconductor as a variable capacitor for fine tuning of each band. Single N-type metal–oxide–semiconductor switch is placed on secondary side of transformer which makes the transformer tunable. Figure of merit of the proposed circuit is −183.3 dBc/Hz. Proposed VCO provides wide FTR and acceptable low phase noise for V-band application.

25–34 GHz Single-Pole, Double-Throw CMOS Switches for a Ka-Band Phased-Array Transceiver

This paper presents two single-pole, double-throw (SPDT) mm-wave switches for Ka-band phased-array transceivers, fabricated with a 65-nm complementary metal oxide semiconductor (CMOS) process. One switch employs cross-biasing (CB) control with a single supply, while the other uses dual-supply biasing (DSB) control with positive and negative voltages. Negative voltages were generated internally, using a ring oscillator and a charge pump. Identical gate and body floated N-type metal oxide semiconductor field effect transistors (N-MOSFETs) in a triple well were used as the switch core transistors. Inductors were used to improve the isolation between the transmitter (TX) and receiver (RX), as well as insertion loss, by canceling the parasitic capacitance of the switch core transistors at resonance. The size of the proposed radio frequency (RF) switch is 260 μm × 230 μm, excluding all pads. The minimum insertion losses of the CB and DSB switches were 2.1 dB at 28 GHz and 1.93 dB at 24 GHz, respectively. Between 25 GHz and 34 GHz, the insertion losses were less than 2.3 dB and 2.5 dB, the return losses were less than 16.7 dB and 17.3 dB, and the isolation was over 18.4 dB and 15.3 dB, respectively. The third order input intercept points (IIP3) of the CB and DSB switches were 38.4 dBm and 39 dBm at 28 GHz, respectively.

Radiation effect and degradation mechanism in 65 nm CMOS transistor

Radiation effect of deep submicron semiconductor device has been extensively studied in recent years. However, fewer researches laid emphasis on the degradation characterization induced by total ionizing dose (TID) damage in nano-device. The purpose of this paper is to analyze the TID effect on the 65 nm commercial complementary metal oxide semiconductor transistor. The n-type and p-type metal oxide semiconductor field effect transistors (NMOSFET and PMOSFET) with different sizes are irradiated by 60Co γ rays at 50 rad (Si)/s, and TID is about 1 Mrad (Si). Static drain-current ID versus gate-voltage VG electrical characteristics are measured with semiconductor parameter measurement equipment. The irradiation bias of NMOSFET is as follows:the ON state is under gate voltage VG=+1.32 V, drain voltage VD is equal to source voltage VS (VD=VS=0), and the OFF state is under drain voltage VD=+1.32 V, gate voltage VG is equal to source voltage VS (VG=VS=0). The irradiation bias of PMOSFET is follows:the ON state is under gate voltage VG=0 V, drain voltage VD is equal to source voltage VS (VD=VS=1.32 V), and the OFF state is under VD=VG=VS=+1.32 V. The experimental results show that the negative shifts in the threshold voltage are observed in PMOSFET after irradiation. Besides, for PMOSFET the degradation of the ON state during radiation is more severe than that of the OFF state, whereas comparatively small effect are present in NMOSFET. Through experimental data and theoretical analysis, we find that the changes in the characteristics of the irradiated devices are attributed to the building up of positive oxide charges in the light doped drain (LDD) spacer oxide, rather than shallow trench isolation oxide degradation. The positive charges induced by TID in PMOSFET LDD spacer oxide will lead to the change of hole concentration in channel, which causes the threshold voltage to shift. What is more, the difference in electric field in the LDD spacer is the main reason for the difference in the radiation response between the two radiation bias conditions. Radiation-enabled technology computer aided design used to establish two-dimensional mode of the transistor. The simulation results of ID-VG curves are in good agreement with the experimental results. Combining theoretical analysis and numerical simulation, the radiation sensitive regions and the damage physical mechanism and radiation sensitivity regions of PMOSFETs are given. This work provides the helpful theory guidance and technical supports for the radiation hardening of the nano-devices used in the radiation environments.

Direct Measurement of Active Near-Interface Traps in the Strong-Accumulation Region of 4H-SiC MOS Capacitors

This brief presents direct electrical measurement of active defects in the strong-accumulation region of N-type 4H-SiC MOS capacitors, which corresponds to the strong-inversion region of N-channel MOSFETs. The results demonstrate the existence of an active defect in the gate oxide, located very close to the SiC surface, with localized energy levels between 0.13 eV and 0.23 eV above the bottom of the conduction band. The observed spatial and energy localizations indicates that this is a well-defined defect.

A novel fabrication method for co-integrating ISFET with damage-free sensing oxide and threshold voltage-tunable CMOS read-out circuits

A novel fabrication method using a top SiO2-SiN-bottom SiO2 (ONO) dielectric stack is proposed and implemented to obtain ion sensitive field effect transistor (ISFET) with damage-free sensing oxide and threshold voltage (Vth)-tunable devices in CMOS read-out circuits. By wet-etching the top SiO2 and the SiN sequentially, the ISFET with damage-free sensing oxide is obtained due to the high selectivity between them. Also, the Vth-tunable circuit devices with the ONO stacks are simultaneously achieved by protecting the ONO stacks from the wet-etching. Through the measurements of pH and biomolecule responses, it is confirmed that the pH and biomolecule can be detected stably because the drain current (ID) is stabilized to a predetermined value more quickly and the ID fluctuation during the ID stabilization is significantly reduced compared with devices having damaged sensing oxide. Additionally, it is verified that the Vth of devices for circuits can be fine-controlled by injecting charges into the SiN via Fowler-Nordheim tunneling. Furthermore, it is demonstrated that the biomolecule-induced Vth shift of ∼150 mV in the proposed ISFET is successfully amplified to the output voltage change of ∼370 mV in common source amplifier (CSA) voltage-readout circuit consisting of one p-type ISFET and one Vth-tuned n-type MOS.