N-type Metal-oxide-semiconductor Research Articles

Charge Pumping Under Spin Resonance in Si(100) Metal-Oxide-Semiconductor Transistors

Gate-pulse-induced recombination, known as the charge pumping (CP), is a fundamental carrier recombination process, and has been utilized as a method for analyzing electrical properties of defects (or dangling bonds) at the transistor interfaces, which is now recognized to be well-matured and conventional. Nevertheless, neither the origin (the bonding configuration) of the defects responsible for the CP, nor their detailed recombination sequence has been clarified yet for Si metal-oxide-semiconductor (MOS) interfaces. In order to address these problems, we investigated the CP under spin resonance conditions at temperatures ranging from 27 to 300 K in Si(100) n-type MOS transistors. We obtained evidence that Pb0 and E' centers, the two major dangling bonds at (and near) the Si(100) interface, participate in the CP recombination process. We also show that the spin-dependent CP process is explained by the formation of electron-electron spin pairs, which in turn reveals that the CP via Pb0 and E' centers is inherently a two-electron process.

Influence of various NO annealing conditions on N-type and P-type 4H-SiC MOS capacitors

NO post-oxidation annealing (POA) processes with different temperatures and durations are simultaneously studied on the n-type and p-type 4H-SiC MOS capacitors. The results from Secondary Ion Mass Spectroscopy (SIMS) reveal that nitrogen diffuses further into the SiO2 layer for the samples annealed at higher temperature (1250 °C). Furthermore, the area densities of nitrogen for the n-type samples are about 1.3 times larger than the p-type samples. The densities of negative effective fixed dielectric charge (Neff) and slow-state electron traps are effectively decreased with increasing annealing time and temperature for the n-type samples. However, the introduced nitrogen leads to more the deep energy-level traps [0.5–0.6 eV above the valence band edge (Ev)] in the p-type samples, which can exchange electrons with near-interface traps in response to the alternating current (AC) signal below 10 kHz. Besides, the densities of the slow-state hole traps, which are obviously increased at low temperature but raised slowly at high temperature, are mainly affected by the temperature of the NO POA process and not only the density of incorporated nitrogen. Therefore, NO annealing at high temperature with a short duration (at 1250 °C 1 h) may be a good choice to optimize NO POA treatment for n-channel 4H-SiC MOSFETs, based on comprehensive consideration of the influence of different NO POA conditions on n-type and p-type MOS capacitors.

Energy-Localized Near-Interface Traps Active in the Strong-Accumulation Region of 4H-SiC MOS Capacitors

Near-interface traps (NITs) with energy levels aligned to the conduction band and spatially located close to the SiO2/SiC interface are responsible for significant degradation of the channel-carrier mobility in 4H-SiC MOSFETs. In this paper, we investigate fast trapping and detrapping of the conduction-band electrons by NITs with energy levels localized between 0.13 and 0.23 eV above the bottom of the conduction band. The trapping and detrapping times were estimated to be in the range between the resolution limit of tens of nanoseconds and $1~\mu \text{s}$ by measuring the current through n-type MOS capacitors in response to a ramped voltage in the accumulation region.

Detection and Cryogenic Characterization of Defects at the SiO2/4H-SiC Interface in Trench MOSFET

We employed the thermal dielectric relaxation current (TDRC) method for the detection and cryogenic characterization of traps at the 4H-SiC/SiO2 interface in n-channel trench MOSFETs and n-MOS trench capacitors. The interface of trench devices on the ( $\textsf {11}\overline {2}\textsf {0}$ )-plane atomically differs from the interface of standard lateral devices [(0001)-plane]. In the MOSFET, two TDRC signal peaks originating from electron traps were found and characterized by parameter variation in TDRC measurements. One peak corresponds to interface states located 0.13 eV below the 4H-SiC conduction band edge EC. The other one is attributed to the near-interface traps (NITs) with an electron emission barrier of 0.3 eV. The NIT peak shows an inverse dependence on the discharging voltage compared to regular interface states. In contrast to the MOSFET, only NITs were measured in n-type MOS capacitors. The results found in trench devices were also confirmed for lateral devices. Therefore, we show that the study of SiC MOS capacitors is not sufficient for the understanding of degradation mechanisms in SiC MOSFETs. The interface states at EC-0.13 eV detected in MOSFETs are assumed to contribute to the degradation of the apparent channel mobility and ON-resistance of SiC MOSFETs. These states are strongly reduced by annealing in NO compared to N2.

Photoelectrochemical Water Splitting with p-Type Metal Oxide Semiconductor Photocathodes.

Photoelectrochemical (PEC) water splitting is a promising way to produce clean and sustainable hydrogen fuel. Solar hydrogen production by using p-type metal oxide semiconductor photocathodes has not been studied as extensively as that with n-type metal oxide semiconductor photoanodes and p-type photovoltaic-grade non-oxide semiconductor photocathodes. Copper-based oxide photocathodes show relatively good conductivity, but suffer from instability in aqueous solution under illumination, whereas iron-based metal oxide photocathodes demonstrate more stable PEC performance but have problems in charge separation and transport. Herein, an overview of recent progress in p-type metal oxide-based photocathodes for PEC water reduction is provided. Although these materials have not been fully developed to reach their potential performance, the challenges involved have been identified and strategies to overcome these limitations have been proposed. Future research in this field should address these issues and challenges in addition to the discovery of new materials.

A Sub-fs-FoM Digital LDO Using PMOS and NMOS Arrays With Fully Integrated 7.2-pF Total Capacitance

A digital low-dropout (DLDO) regulator using p-type MOS (PMOS) and n-type MOS (NMOS) switches is proposed to achieve a sub-fs speed figure-of-merit (FoM) by reducing the total capacitance ( $C_{\mathrm {TOT}}$ ) and accomplishing a comparable output voltage droop ( $\Delta V_{\mathrm {OUT}}$ ) during a load transition. The proposed DLDO uses the segmented PMOS switches to fully turn on the NMOS array, which strengthens the intrinsic NMOS loop and maintains the undershoot and overshoot voltages of 88 and 42 mV, respectively, during an 88.4-mA load transition. In addition, with the aid of the proposed voltage doubler (VD)-based periodically refreshed level shifter (PRLS), the total capacitance of DLDO to drive NMOS array is reduced to 7.2 pF, which is 3.3 $\times $ smaller than that of previous work, extending the input voltage ( $V_{\mathrm {IN}}$ ) and load current ( $I_{\mathrm {LOAD}}$ ) ranges up to 0.9 V and 140 mA, respectively. The proposed DLDO is fabricated using a 28-nm CMOS process and achieves a 0.12-fs speed FoM that is 42.5 $\times $ smaller than the state-of-the-art designs.

Low temperature atomic layer deposition of zirconium oxide for inkjet printed transistor applications.

We report the growth of zirconium oxide (ZrO2) as a high-k gate dielectric for an inkjet-printed transistor using a low-temperature atomic layer deposition (ALD) from tetrakis(dimethylamido)zirconium (TDMAZr) and water precursors. All the samples are deposited at low-temperature ranges of 150–250 °C. The films are very uniform with RMS roughness less than 4% with respect to their thickness. The atomic force microscopy (AFM) shows a significant change in surface morphology from tapered posts to undulating mountain-like structures with several hundreds of ALD cycles. The results from X-ray diffraction (XRD) analysis exhibit an amorphous to the crystalline structure with temperature variation, which is independent of the thickness of the films. All our samples are hydrophilic as contact angles are less than 90°. The capacitance–voltage (C–V) and conductance–voltage (Gp/ω–V) characteristics of ZrO2 dielectrics for silicon metal–oxide–semiconductor (MOS) capacitors are studied for different temperatures. For the n-type substrate MOS capacitors, the dielectric constants are estimated to be 7.5–11. Due to the low deposition temperature, a hydrophilic surface, and high k value, the ALD-ZrO2 dielectric can be compatible for printed transistors. The processes of fabrication and characterization of inkjet-printed graphene transistors is demonstrated using the ZrO2 dielectric. The possible solvents, surfactant, and the dielectric induced modifications in graphene flakes are demonstrated by Raman spectra. The graphene flakes spread uniformly on the ZrO2 surface. The functional inkjet-printed graphene transistor characteristics are demonstrated to illustrate the field effect behavior with the ALD-ZrO2 dielectric.

Layout Modification of a PD-SOI n-MOSFET for Total Ionizing Dose Effect Hardening

A dummy-gate-assisted n-type metal–oxide–semiconductor field-effect transistor (DGA n-MOSFET) structure was modified to allow the use of a silicon-on-insulator (SOI) substrate and evaluated for robustness against the total ionizing dose effect. The modified DGA n-MOSFET on the SOI substrate suppressed all possible radiation-induced leakage current paths by isolating both the drain and source from the sidewall oxide using a p+ layer and from the buried oxide using dummy gates and halo doping. Simulated ${V} _{\textsf {g}}$ – ${I} _{\textsf {d}}$ curves indicated that the modified DGA n-MOSFET on the SOI substrate effectively reduces the leakage current caused by accumulated radiation exposure. Furthermore, experimental gamma radiation exposure data showed that the modified device exhibited good performance, even after exposure up to 300 krad (Si). All devices used in the experiments were fabricated using the 180-nm commercial fabrication process by the CSOI7RF of Global Foundries, formerly IBM Microelectronics.

Abnormal Positive Bias Temperature Instability Induced by Dipole Doped N-Type MOSCAP

This work performs fundamental electrical measurements and a positive bias temperature instability (PBTI) test on an N-type metal oxide semiconductor capacitor (MOSCAP) and a La2O3 dipole-doped N-type MOSCAP. Experimental results show that the dipole-doped N-type MOSCAP has a lower threshold voltage and gate current leakage than do the N-type MOSCAP. After positive bias stress, an abnormal gate current leakage decrease appears in both dipole-doped and normal N-type MOSCAPs under short term stress. Analysis of capacitance and gate current measurements indicate that electron trapping and defect generation cause the change in gate current after positive bias stress. Generally, devices with higher gate leakage have more severe degradation after PBTI. However, in this work, the dipole sample shows a lower initial gate current leakage but higher gate current degradation than those found in the control sample after PBTI. Based on the electrical measurement results and the energy band simulation, a conduction model was proposed to explain the abnormal PBTI of the dipole-doped N-type MOSCAP.

Characterization of high mobility inverted coplanar Zinc Nitride Thin-film Transistors

In this work, high mobility TFTs based on zinc nitride (Zn3N2) sputtered at room temperature using spin-on glass (SOG) as gate dielectric are presented. The inverted coplanar structure is used for the Zn3N2 TFTs. The devices exhibit an on/off-current ratio of 106 and a subthreshold slope of 0.88 V/decade. The extracted field-effect mobility was 15.8 cm2/Vs which is among the highest reported for Zn3N2 TFTs. In addition, n-type MOS capacitors were fabricated and characterized by capacitance – voltage and capacitance – frequency measurements to evaluate the dielectric characteristics of the SOG film.

Study on the effect of growth-time and seed-layers of Zinc Oxide nanostructured thin film prepared by the hydrothermal method for liquefied petroleum gas sensor application

Gas sensors are devices that can convert the concentration of an analytic gas into an electronic signal. Zinc oxide (ZnO) is an important n-type metal oxide semiconductor which has been utilized as gas sensor for several decades. In this work, ZnO nanostructured films were synthesized by a hydrothermal route from ZnO seeds and used as a liquefied petroleum gas (LPG) sensor. At first ZnO seed layers were deposited on glass substrates by using spin coating method, then ZnO nanostructured were grown on these substrates by using hydrothermal growth method for different time duration. The effect of growth time and seed layers of ZnO nanostructured on its structural, optical, and electrical properties was studied. These nanostructures were characterized by X-ray diffraction, scanning electron microscopy, optical spectroscopy, and four probes sheet resistance measurement unit. The sensing performances of the synthetic ZnO nanostructures were investigated for LPG.XRD showed that all the ZnO nanostructures were hexagonal crystal structure with preferential orientation. SEM reviled that the size of nanostructure increased with increase in growth time. Band gap and sheet resistance for ZnO nanostructured thin film decreased with increase in growth time. ZnO nanostructured thin film showed high sensitivity towards LPG gas. The sensitivity of the film is observed to increase with increase in no of seed layers as well as growth time. The dependence of the LPG sensing properties on the different growth time of ZnO nanostructured was investigated. The sensing performances of the film were investigated by measured change in sheet resistance under expose to LPG gas. BIBECHANA 16 (2019) 145-153

Investigation of characteristics and hot-carrier reliability of high-voltage MOS transistors with various doping concentrations in the drift region

The effect of doping concentration in the n− drift region on the characteristics and hot-carrier reliability in high-voltage n-type MOS transistors is investigated. Results show that a proper increase in the n− drift doping concentration improves device characteristics. In addition, a proper increase in the n− drift doping concentration reduces hot-carrier induced device degradation. Technology computer-aided design simulation results suggest that the impact of hot-carrier induced interface charge generation on device degradation is alleviated for a higher n− drift doping concentration. Such a result can explain the reduction in hot-carrier induced device degradation for the device with a higher doping concentration in the n− drift region.

Single chip design for detection and recovery of series LED open/short fault tolerance circuit

Light emitting diode (LED) lighting is widely used in current. However, lighting robustness is low in a series loop since the lighting shuts down as one LED fails. This study proposes a power chip for fault detection and isolation for enhancement of LED's fault-withstanding capability. The chip can automatically detect the failed LEDs and bypass them, and let others continue to work. The authors implemented four bypass loops using a power metal oxide semiconductor (MOS) on the single chip. This chip can drive 1 A with 4-bit current dimming, which includes four bypass power P-type MOSs, one power N-type MOS, schedule controller, level shifter and over voltage protection. The schedule controller with a state machine can quickly find which one LED fail and recover it soon. The prototyping chip was designed using TSMC 0.25 μm, which is the second generator high-voltage technology, and the resulting chip area with pads is only 1.3 × 1.7 mm2. The chip had been successfully implemented and measured to drive and bypass four LED components or modules.

Revealing the Performance-Limiting Factors in α-SnWO4 Photoanodes for Solar Water Splitting

α-SnWO4 is an n-type metal oxide semiconductor that has recently attracted attention as a top absorber material in a D4-tandem device for highly efficient solar water splitting due to the combination of an ideal bandgap (∼1.9 eV) and a relatively negative photocurrent onset potential (∼0 V vs RHE). However, up to now, α-SnWO4 photoanodes have not shown high photoconversion efficiencies for reasons that have not yet been fully elucidated. In this work, phase-pure α-SnWO4 films are successfully prepared by pulsed laser deposition. The favorable band alignment is confirmed, and key carrier transport properties, such as charge carrier mobility, lifetime, and diffusion length are reported for the first time. In addition, a hole-conducting NiOx layer is introduced to protect the surface of the α-SnWO4 films from oxidation. The NiOx layer is found to increase the photocurrent for sulfite oxidation by a factor of ∼100, setting a new benchmark for the photocurrent and quantum efficiency of α-SnWO4. These results p...

Growth and characterization of nitrogen-phosphorus hybrid passivated gate oxide film on N-type 4H-SiC epilayer

A novel nitrogen-phosphorus (N&P) hybrid passivation technique by NO-containing dry oxidation of phosphorus-implanted 4H-SiC epilayer has been proposed to grow high-property gate oxide film. For demonstration and contrast, n-type 4H-SiC MOS capacitors with N&P hybrid and only N passivation have been fabricated and tested. The results from Secondary Ion Mass Spectroscopy (SIMS) reveal that about 60% of the implanted phosphorus atoms remain in the SiO2 film after sacrificial oxidation of the implantation layer. And the distribution of phosphorus is approximately uniform throughout the grown SiO2 film with a concentration about 4 × 1019 cm−3, avoiding the SiO2 film converting to phosphosilicate glass (PSG). I-V and X-ray Photoelectron Spectroscopy (XPS) data show that the grown SiO2 film with the appropriate phosphorus passivation can effectively improve the quality of oxide film, leading the gate oxide bandgap and integrity improved and reducing the leakage current above two orders of magnitude. The bias stress measurements with ultraviolet light (UVL) irradiation also show that the N&P hybrid passivation treatment can completely restrain the near-interface electron traps (NIETs) in 4H-SiC MOS devices, indicating that incorporation an appropriate amount of phosphorus atoms in the grown SiO2 film also can make the electron trap density reduced effectively.

Total ionizing dose and single event effects of 1 Mb HfO2-based resistive-random-access memory

Experiments of total ionizing dose (TID) using a Cobalt-60 source and single event effects (SEE) using pulsed laser and heavy ion were conducted to investigate the radiation effects in 1 Mb HfO2-based resistive-random-access memory (RRAM) with 1T1R (1 access transistor in series with 1 RRAM) storage cell structure. TID-induced leakage current in the access transistors on the same bit-lines caused a read decision failure and the bit errors observed. The failure threshold for the leakage current of access transistor was about 3.4 nA by HSpice simulation, which was also verified by the transfer characteristics of the access N-type Metal-Oxide-Semiconductor (NMOS) transistor in 1T1R cell before and after radiation. The RRAM array was immune to single event upsets (SEU) regardless of the pulsed laser and heavy ion used. The single event latchup (SEL) in row decoder circuits was found to trigger burst of errors, whose physical mapping was analyzed. These analyses and finds are useful for developing radiation-hard RRAM aimed at space applications.

A CMOS Follower-Type Voltage Regulator With a Distributed-Element Fractional-Order Control

This paper presents an application of a fractional-order control in an on-chip follower-type 1.8 V/100 mA voltage regulator to achieve a good stability with any load capacitance. The controller approximates an integrator with the fractional order of 0.5, whose phase lag is not more than 45°. The fractional order is set by the fractional-order impedance of the resistive p-type MOS capacitor (R-PMOScap). With an n-type MOS source follower stage adding the phase lag of at most 90°, the remaining phase margin is always at least 45°. The R-PMOScap is a novel integrated distributed-element RC network, realized as a resistive polysilicon strip on a gate oxide, and is compatible with an analog CMOS process. The voltage regulator has been manufactured in a 350-nm CMOS process and occupies a small chip area of 0.038 mm2. It operates in a harsh automotive environment with a temperature from −50 °C to 200 °C and shows a tight DC regulation, while being stable over the full range of the load current (from 0 to 100 mA) and with any load capacitance (allowing to use none or any external capacitor).

Low-temperature sol-gel ZrHfO2-PMMA hybrid dielectric thin-films for metal oxide TFTs

In this work, we developed a novel inorganic-organic hybrid gate dielectric by combining zirconium and hafnium components to form zirconium hafnium oxide strongly linked with polymethyl methacrylate (ZrHfO2-PMMA) and deposited at low temperature (200 °C) by sol-gel method. The obtained 108 nm thick, high-quality hybrid gate dielectric showed an exceptionally low surface roughness (0.9-nm), a low leakage current density (7.7 × 10−6 A/cm2) and reasonable dielectric properties such as gate capacitance along with dielectric constant (77 nF/cm2 & 9.4 @1 kHz) respectively. To examine the ZrHfO2-PMMA hybrid dielectric electrical properties we constructed thin-film transistors (TFTs) with room temperature r.f sputtered n-type metal oxide semiconductors, a-IGZO and ZnO, as active channels. The bottom gate fabricated a-IGZO TFTs driving at as low as below 6 V, with extracted field effect mobility of 2.45 cm2/V. s, a low threshold voltage of 1.2 V with large ON/OFF current ratio 107 respectively. On the other hand, for comparison we employed ZnO TFTs by applying same hybrid dielectric system, the obtained parameters of bottom gate ZnO TFTs were good field effect saturation mobility of 12.8 cm2/V. s, threshold voltage of 1.8 V and ON/OFF current ratio of 103.

An Improved Hot-Carrier Lifetime Evaluation Method for the n-Type LDMOS With Hot-Hole Injection

The hot-carrier lifetime evaluation method of a 90-V-level n-type lateral double-diffused MOS (LDMOS) is investigated in this brief. Our charge pumping experiments demonstrate that the on-resistance degradation of the device is induced by the combination effect of the hot-hole injection at field oxide region and the interface state generation at field oxide and accumulation regions. Thereby, the hot-carrier lifetime of the device was evaluated by the comprehensive model proposed by Moens, which considers the effects of both hot-hole injection and the interface state generation. However, our experiments found that multiple lifetimes were obtained based on the model proposed by Moens and some lifetimes have the risk of overestimation. To solve the problem, an improved hot-carrier lifetime evaluation method based on a novel semiempirical model is proposed. Further experiments and analyses illustrate that the proposed hot-carrier lifetime evaluation method can provide a definite lifetime that has no risk of overestimation for the investigated LDMOS and has improved the lifetime prediction precision compare to the method based on Hu’s model.

(Invited) New p-Type Oxide Semiconductor with High Hole Mobility over 7 cm2/Vs Formed By Solution Process

We report new p-type metal oxide semiconductor thin-film transistor with high field-effect hole mobility fabricated in solution process in this work. Metal oxide semiconductors have long attracted large attention as large-area electronic devices by virtue of high electrical and optical performances such as transparency, large electron mobility, good uniformity and low-temperature processability since the pioneering work of Prof. Hosono group in 2004, and their mass production has now been successfully realized in the active matrix backplane of flat-panel or flexible display. Few p-type metal oxide semiconductors with high performance, however, have been reported compared with n-type metal oxide semiconductors such as InGaZnO, InZnSnO, etc. This is mostly ascribed as the localization of valence band maximum which mainly consists of oxygen p orbitals. To enhance the dispersion of valence band, it has been theoretically proposed that the filled diffuse metal d or s orbital to hybridize with oxygen 2p orbital can be utilized and indeed it was experimentally demonstrated that Sn 5s orbital and Cu 3d orbital played such a role in SnO and CuO, respectively. But, SnO phase is very vulnerable to disproportion reaction to metallic Sn and SnO2 which behaves as an n-type semiconductor so that the process window to realize it in electron devices was very narrow and the electrical performance in the devices such as thin-film transistor was very limited, e.g low on/off ratio. Inspired by the theoretical work of high throughput materials screening performed by the first principles calculation, we fabricated the alkali metal doped SnO thin-film with solution process and low-temperature annealing less than 400 oC. We found that the oxidation state of Sn in thin-films changed from +4 state (SnO2 phase) to +2 state (SnO phase) depending on the content of alkali metal ions from x-ray photoelectron spectroscopy (XPS). Furthermore, Hall-effect measurement indicated the type conversion of the majority carrier from n-type to p-type as the content of alkali metal ion increases, in consistence with XPS results. The high hall mobility of 51 cm2/Vs was obtained at the optimal alkali-metal ion doped SnO thin film and we successfully fabricated thin-film transistors with alkali-metal ion doped SnO with a field-effect hole mobility over 7 cm2/Vs. We hope that this work will contribute to open a new era for transparent large area electronics based on oxide semiconductors with high functionalities such as complementary logic circuit.