Detection and Cryogenic Characterization of Defects at the SiO2/4H-SiC Interface in Trench MOSFET

Abstract

We employed the thermal dielectric relaxation current (TDRC) method for the detection and cryogenic characterization of traps at the 4H-SiC/SiO2 interface in n-channel trench MOSFETs and n-MOS trench capacitors. The interface of trench devices on the ( $\textsf {11}\overline {2}\textsf {0}$ )-plane atomically differs from the interface of standard lateral devices [(0001)-plane]. In the MOSFET, two TDRC signal peaks originating from electron traps were found and characterized by parameter variation in TDRC measurements. One peak corresponds to interface states located 0.13 eV below the 4H-SiC conduction band edge EC. The other one is attributed to the near-interface traps (NITs) with an electron emission barrier of 0.3 eV. The NIT peak shows an inverse dependence on the discharging voltage compared to regular interface states. In contrast to the MOSFET, only NITs were measured in n-type MOS capacitors. The results found in trench devices were also confirmed for lateral devices. Therefore, we show that the study of SiC MOS capacitors is not sufficient for the understanding of degradation mechanisms in SiC MOSFETs. The interface states at EC-0.13 eV detected in MOSFETs are assumed to contribute to the degradation of the apparent channel mobility and ON-resistance of SiC MOSFETs. These states are strongly reduced by annealing in NO compared to N2.