Multi-threshold Voltage Research Articles

Investigation of dual work function metal (DWFM) gate stacks with ALD TaAlN and TaAlC for multi threshold voltages (VTHs) engineering in MOS device integration

This study investigates methods to modulate the effective work function (EWF) and control the multiple threshold voltages (VTHs) of metal-oxide-semiconductor (MOS) devices by applying metal electrodes with different work function materials (WFMs), including a single layer of n-type (TaAlC) and p-type (TaAlN) as well as their stacked structures, through atomic layer deposition (ALD). Dual-Work-Function-Metal (DWFM) gate is a crucial aspect of confirming the feasibility of metal gate stacks in MOS devices for a complementary metal-oxide-semiconductor (CMOS) integration scheme. The gate stack structure of p-Si/IL (Inter layer)/HfO2/DWFM (p/n-type compatible metal stack)/W exhibits good adhesion and even chemical composition distribution, as evidenced by transmission electron microscope (TEM) and energy dispersive spectrometer (EDS) analysis. By fabricating MOS capacitors using this WFM structure and extracting EWF from the measured capacitance-voltage (C–V) characteristics, EWF values of 4.62 eV and 4.99 eV were identified both before and after annealing using forming gas, indicating pWFM-like properties. These properties are attributed to the strengthened Al–O bonds and reduced CO peaks seen in x-ray photoelectron spectroscopy (XPS) analysis. The use of different Ta precursor from Tris(diethylamido)(tert-butylimido)tantalum(V) (TBTDET) as well as TaCl5 resulted in the increase of the EWF following the unique p-WFM like feature. As candidates for WFM electrode in metal-oxide-semiconductor field effect transistor (MOSFET) with the DWFMs (n/p stacks) were evaluated, resulting in a VTH of 0.84 V that places in the middle of the VTH shift range from 0.6 V (nWFM) to 1.16 V (pWFM), approximately. The DWFMs allow for modulation of the EWF, which in turn reduces ambiguity in addressing replacement metal gate (RMG) challenges and opens up new avenues for achieving multi-VTH solutions in CMOS integration schemes.

Source of IC power consumption and low power design

In these years, with the continuous development of 14nm and 7nm chip processes and the increasing popularity of computers, cell phones, and smart homes, the growing market of electronic products and ultra-fine research for the reliability of the chip requirements gradually increased. The method of reducing power consumption in the new context of new technology is called the chip field die-cut concern. This paper mainly summarizes two aspects of power consumption sources and methods to reduce power consumption, to provide a reference basis for future research directions: First, the major sources of power consumption are static power consumption and dynamic power consumption. The primary sources of static power consumption are sub-threshold leakage and gate leakage current. This paper also mentions some other leakage currents, such as reverse bias PN junction current and induced leakage current, which can be more carefully considered when exploring methods to reduce power consumption. A more comprehensive consideration when exploring ways to reduce power consumption. Dynamic power consumption is mainly divided into Switching power and Internal power and short-circuit power. Then we summarize the existing methods which can reduce power consumption: Clock gating (including Clock gating without a latch and Clock gating with a latch), Dynamic voltage and frequency scaling, multi-supply and multi-voltage technology, Power gating and multi-threshold voltage. These methods are from a proprietary perspective to reduce power consumption.

A power/energy-efficient, process-variation-resilient multiplier using graphene nanoribbon technology and ternary logic

In consideration of the difficulties related to interconnectivity and energy usage in binary logic, designers have felt compelled to explore ternary logic as a viable alternative. The most effective approach for implementing circuits based on ternary logic involves the use of the multi-threshold voltage (Vth) technique. In the case of field-effect transistors (FETs) that utilize graphene nanoribbons (GNRs), known as GNRFETs, the value of Vth relies on the GNR’s width, which can be adjusted by altering the dimer lines number. GNRFET shows potential as a replacement for CMOS technology due to the remarkable properties of GNR that help address scaling issues and short-channel effects. However, for real-time applications like portable electronic devices, power and energy efficiency are the primary concerns. Consequently, this paper presents a power and energy-efficient ternary multiplier based on 32-nm GNRFET technology. HSPICE simulation results obtained at 0.9 V demonstrate that the suggested circuit can achieve a minimum of 36.72% improvement in power and 28.17% enhancement in energy efficiency. This is accomplished through the utilization of distinct methods such as specific transistor configurations, unary operators, and dual power sources. Moreover, Monte-Carlo simulation results confirm the variation tolerance of the proposed circuit.

Design and Optimization of Flywheel Energy Storage System for Rail Transit

At present, the urban rail transit system has problems such as energy waste in the braking process and unstable grid voltage in the start-stop state. Aiming at the problems caused by the start-stop state of rail transit, considering the energy saving and voltage stability requirements of system energy management, a flywheel energy storage system (FESS) specially used for rail transit is designed. The energy system (FESS) can feed back the braking energy stored by the flywheel to the urban rail train power system when the rail train starts to cause the voltage and frequency of the traction microgrid to change. This paper proposes a flywheel energy management system based on a permanent magnet synchronous motor (PMSM), which can realize efficient energy management through efficient control of the flywheel side motor. The flywheel side permanent magnet synchronous motor adopts an improved flywheel speed expansion energy storage control strategy based on current feedforward control to improve the fast response capability of the flywheel, ensuring the output power of the flywheel at high speed. In addition, a specific multi-threshold voltage single FESS control strategy is suggested, which improves the energy-saving and voltage-stabilizing performance of the system.

Analysis of 7T SRAM Cell Based on MTCMOS, SVL and I-SVL Technique

Objective: To design and propose an optimized Volatile 7T based SRAM cell in terms of leakage currents and dynamic power. Methods: The methodology involved is Multi threshold Voltage CMOS (MTCMOS), Self Controllable Voltage Level (SVL) and Improved Self Controllable Voltage Level (I-SVL). Findings: The proposed work demonstrates that 7T based SRAM cell using I-SVL method is efficient in terms of leakage currents and dynamic power. Also, Comparative Leakage current and dynamic power analyses are done between MTCMOS, SVL, and I-SVL methods The Proposed work based on I-SVL is significant than the MTCMOS and SVL Technique. All the circuits are developed using the Cadence virtuoso tool and spectre simulator is used to carry out the simulation. Novelty: The paper proposes Low power Volatile Memory cell based on 7T with improvements in leakage and dynamic power values in comparison with the earlier literatures. The proposed I-SVL based cell is 89% and 85% efficient in terms of dynamic power in comparison with the earlier references. Keywords: Improved – Self Controllable Voltage Level (I-SVL); Improved Lower SVL (I-LSVL); Improved Upper SVL (I-USVL); Multi threshold Voltage CMOS(MTCMOS); Self Controllable Voltage Level (SVL); SRAM

Performance Comparison of the Conventional CMOS and MTCMOS Digital Circuits and Their Simulation

This paper focuses on the design of the conventional CMOS digital circuits and the Multi-Threshold CMOS (MTCMOS) digital circuits, which perform the specific Boolean logic function, as well as the comparison between these designing techniques by their functionality and power consummation (dissipation). The leakage of currents in integrated circuits based on CMOS logic becomes quite significant when the complementary MOS transistors are the small-device geometries (small dimensions), and this effect imposes alternative techniques that enable the designing of CMOS digital circuits with low-power dissipation, even in standby mode. One of these techniques is the design of the CMOS digital circuits with multi-threshold voltage (MTCMOS), which enables the reduction of the leakage power dissipation, as a part of the overall power dissipation in CMOS logic. Two CMOS digital circuits are designed (2-input XNOR CMOS gate and the other one is the CMOS gate that performs a complex Boolean function) based on conventional CMOS technique and multi-threshold voltage CMOS technique, and their functionality and calculation of the average overall power dissipation are tested using the Computer-Aided Design (CAD). The methodology used to achieve low power dissipation in CMOS digital circuits (MTCMOS) will be an efficient method for reducing the overall dissipation, while the high speed performance will be maintained.

Optimum sizing of the sleep transistor in MTCMOS technology

Multi-threshold voltage complementary metal-oxide semiconductor (MTCMOS) technology finds a wide variety of applications in reducing the subthreshold-leakage current in both combinational and sequential circuits. This is due to the fact that slightly increasing the threshold voltage causes a dramatic decrease in the subthreshold-leakage current. One of the most important applications of the MTCMOS technology is the use of a sleep transistor with high threshold voltage. However, the decision on the sizing of the sleep transistor is a critical issue because there are various trade-offs that the designer must face with this respect. In this paper, the area, the static and dynamic-power consumption, and the time delay are investigated with respect to the aspect ratio of the sleep transistor with compact-form expressions derived for them. Accordingly, the optimal size of the sleep transistor is determined quantitatively. In addition, a realistic figure of merit (FOM) that takes into account the contradicting parameters when sizing the sleep transistor is introduced and verified by simulations. The results are discussed for various cases of the logic circuit at hand. The results obtained are also verified by simulation adopting the Berkeley predictive technology model (BPTM) of the 45 nm, 32 nm, and 22 nm CMOS technologies with power-supply voltages, VDD, equal to 1 V, 0.9 V, and 0.8 V, respectively.

Ternary logic decoder using independently controlled double-gate Si-NW MOSFETs

A ternary logic decoder (TLD) is demonstrated with independently controlled double-gate (ICDG) silicon-nanowire (Si-NW) MOSFETs to confirm a feasibility of mixed radix system (MRS). The TLD is essential component for realization of the MRS. The ICDG Si-NW MOSFET resolves the limitations of the conventional multi-threshold voltage (multi-Vth) schemes required for the TLD. The ICDG Si-NW MOSFETs were fabricated and characterized. Afterwards, their electrical characteristics were modeled and fitted semi-empirically with the aid of SILVACO ATLAS TCAD simulator. The circuit performance and power consumption of the TLD were analyzed using ATLAS mixed-mode TCAD simulations. The TLD showed a power-delay product of 35 aJ for a gate length (LG) of 500 nm and that of 0.16 aJ for LG of 14 nm. Thanks to its inherent CMOS-compatibility and scalability, the TLD based on the ICDG Si-NW MOSFETs would be a promising candidate for a MRS using ternary and binary logic.

A novel model of binary and ternary Schmitt triggers based on multi-threshold voltage in nanoelectronics

In the recent years, the scaling of the CMOS technology, resulting in further reduction of dimensions, has become a severe challenge. The technology of carbon nanotube transistor (CNFET) is one of the most promising ones to replace CMOS. It is, in fact, expected to be commercialized in the coming years. In this paper, as the first step, a binary Schmitt trigger (Binary-ST) is proposed, in which setting the upper trigger point (UTP) and lower trigger point (LTP) is possible separately by only changing the diameter of nanotubes for the two CNFETs used in the input. On the basis of this feature, two Schmitt triggers are designed: Positive Schmitt trigger (POS-ST), in which UTP and LTP are greater than VDD/2, and the negative Schmitt trigger (NEG-ST), in which UTP and LTP are less than VDD/2. In the second step, due to combining these two binary Schmitt triggers, the first ternary Schmitt trigger(Ternary-ST) in nanoelectronics is introduced. Simulation results using Stanford CNFET model at 32 nm technology suggest that in the proposed binary Schmitt trigger, in addition to simply adjusting the UTP and LTP and high input resistance, PDP and EDP were improved about 18% and 25% respectively, as compared to the best work with CNFET. Also, the first proposed ternary Schmitt trigger in nanoelectronics displayed a correct operation and proper performance. The proposed circuits were evaluated under temperature, load and process variation, thus confirming the proper stability and ternary Schmitt trigger performance is insensitive against PVT variations.

Modifying Threshold Voltages to n- and p- Type FinFETs by Work Function Metal Stacks

High-k metal gate technology improves the performance and reduces the gate leakage current of metaloxidesemiconductor field-effect transistors (MOSFETs). This study investigated four different work function metal (WFM) stacks in the gate of fin field-effect transistors (FinFETs) on the same substrate. These devices not only successfully produced distinct levels of threshold voltages (|Vt|) but also converted n- to p-type features merely by adding p-type WFM in the gate of the MOSFETs. All of the devices satisfied short-channel effects with shrinking channel length. The gate-to-body electric field induced drain leakage due to the nature of bulk FinFETs. However, the n- and p-type gate stacks presented different gate current leakage. For reliability, hot carrier injection (HCI) could have a higher reliability impact than the negative-bias temperature instability (NBTI) for p-MOSFET, although the stress voltage of HCI was roughly half that of the NBTI test. This multi-threshold voltage tuning allows designers to design CMOS and choose the trade-off between low power consumption and high performance on the same platform.

A Novel Technique to Produce Logic ‘1’ in Multi-threshold Ternary Circuits Design

Nowadays, due to the high capabilities of nanotechnology in designing multi-valued logic (MVL) circuits, much research has been done to design MVL circuits in nanotechnology. The use of MVL circuits reduces chip interconnections, thereby decreasing the chip area and power consumption. Various methods have been proposed to produce logic ‘1’ in the ternary logic circuits; these include the use of voltage division on VDD and application of two supply voltages. The use of two supply voltages increases the interconnections, which is against one of the multi-valued logic aims, and using voltage division on VDD can cause considerable static power dissipation. In this paper, based on the multi-threshold voltage of CNFET, the circuits are designed to charge a load capacitor to VDD/2 or discharge to VDD/2 in order to produce logic ‘1’ by a novel structure of diode-connected transistors. Thus, with the use of the single-supply voltage, the direct current is eliminated and the static power consumption is dropped sharply. As expected, the simulation results show that the proposed designs have considerably low power consumption with the same delay; thus, they offer a considerably lower PDP in comparison with other single-supply designs with the same noise margin.

A Novel Low-Complexity and Energy-Efficient Ternary Full Adder in Nanoelectronics

Using multi-valued logic can lead to reducing the interconnections in the chip. Reducing the interconnection, in turn, leads to decreasing the chip area and interconnections power dissipation. The design of the multi-valued logic circuits should be performed with the minimum complexity to fulfill the multi-valued logic aim. In the recent years, much research has been focused on the design of multi-valued logics in nanoelectronics due to the high capability of nanoelectronics to design them. In this paper, first, a novel single-supply ternary successor and predecessor are designed based on the multi-threshold voltage in CNFET, which is more energy efficient than those in the previous works. Then, these are used to design the ternary full adder. To reduce the number of transistors in the proposed full adder, the structure of this full adder is designed so that only one successor and predecessor are used and some common portions can be used in the sum and carry generator, and this is shown by equations. The number of transistors in the proposed single-supply full adder is reduced from 132 in the best previous single-supply full adder to 54. Also, to enhance the PDP, the successor and predecessor are used in the quad-state mode (‘0’, ‘1’, ‘2’ and ‘z’: high impedance), where in the ‘z’ mode, the direct current path is cut off. The circuits are simulated by the HSPICE software, using the Stanford 32 nm CNTFET library. The simulation results confirm the correct operation of the proposed circuit and PDP improvement in the proposed ternary full adder, which is about 81.12%, as compared to the best single supply reported in the previous works.

High Performance - Low Leakage Power for SoC Integration Using Multi-Threshold Voltage (Muti-Vt) Library

High Performance - Low Leakage Power for SoC Integration Using Multi-Threshold Voltage (Muti-Vt) Library

Multi-digit Binary-to-Quaternary and Quaternary-to-Binary Converters and Their Applications in Nanoelectronics

Using the multi-valued logic causes the reduction in interconnections, thereby leading to the reduction in chip area and interconnection power dissipation. In order to take advantage of the multi-valued logic, the structure of a mixed-radix system using multi-valued and binary logic is more suitable than that of only using the multi-valued logic; so, the design of a multi-digit converter is necessary. In this paper, first, a new efficient quaternary-to-binary converter and a binary-to-quaternary converter based on multi-threshold voltage are designed using carbon nanotube field effect transistor (CNTFET). Then, multi-digit quaternary-to-binary and binary-to-quaternary algorithms are discussed and implemented. Subsequently, these converters are used in a multi-digit quaternary adder. It is shown that, if quaternary numbers are initially converted into binary numbers and then summation is performed (by using multi-digit quaternary-to-binary and binary-to-quaternary converters), the complexity is considerably reduced, as compared with using the quaternary full adders. Also, some other applications of these converters are discussed. The simulation results using the Stanford 32-nm CNTFET model in the HSPICE software at 0.9 V indicate the correct operation and the high performance of the proposed designs.

Tunnelling-based ternary metal–oxide–semiconductor technology

The power density limits of complementary metal–oxide–semiconductor (CMOS) technology could be overcome by moving from a binary to a ternary logic system. However, ternary devices are typically based on multi-threshold voltage schemes, which make the development of power-scalable and mass-producible ternary device platforms challenging. Here we report a wafer-scale and energy-efficient ternary CMOS technology. Our approach is based on a single threshold voltage and relies on a third voltage state created using an off-state constant current that originates from quantum-mechanical band-to-band tunnelling. This constant current can be scaled down to a sub-picoampere level under a low applied voltage of 0.5 V. Analysis of a ternary CMOS inverter illustrates the variation tolerance of the third intermediate output voltage state, and its symmetric in–out voltage-transfer characteristics allow integrated circuits with ternary logic and memory latch-cell functions to be demonstrated. Quantum-mechanical band-to-band tunnelling can be used to create an energy-efficient ternary logic technology that can be fabricated on the wafer scale using complementary metal–oxide–semiconductor (CMOS) processes.

A Novel Very Low-Complexity Multi-valued Logic Comparator in Nanoelectronics

Using multi-valued logic (MVL) can reduce chip connections, which can have a direct effect on the chip area and connections power consumption. In the recent years, due to the high capability of nanotechnology in designing MVLs, some researchers have focused on this field. In designing MVL circuits, the low-complexity design is of great importance to fulfill the MVL aim. In this paper, a very low-complexity comparator for the MVL is proposed based on the multi-threshold voltage in CNTFETs. The proposed comparator in the 1-bit greater function only needs four transistors for all multi-valued logics; this results in a considerable transistor count reduction in comparison with the pervious works relying on 32 and 50 transistors in a ternary to quaternary case, respectively. Also, the number of 1-bit comparators is reduced from 50 and 74 transistors for the ternary to quaternary cases in the previous works to 12 in the proposed design. Additionally, the multi-digit comparator using the novel digit comparator is proposed. The simulation results using the Stanford 32 nm CNTFET library in HSPICE confirm the proper operation of the proposed comparator with the same range in PDP, in comparison with the previous works.

Ultra‐low‐voltage GDI‐based hybrid full adder design for area and energy‐efficient computing systems

In recent years, ultra-low-voltage (ULV) operation is gaining more importance for achieving minimum energy consumption. Full adder is the basic computational arithmetic block in many of the computing and signal/image processing applications. Here, a new hybrid 1-bit full adder circuit which employs both Gate Diffusion Input (GDI) logic and multi-threshold voltage (MVT) transistor logic is reported. The main objective of the proposed MVT-GDI-based hybrid full adder design is to provide minimum energy consumption with less area. The proposed hybrid design is simulated using standard 45 nm CMOS process technology at an ULV of 0.2 V. The post-layout simulation results have shown that the proposed design achieved significant improvements in comparison with the other reported designs by achieving >57%, 92% savings in the Energy and EDP, respectively, with only 14 transistors. Monte–Carlo simulations have also been performed and is found that the proposed design methodology yields full functionality and robustness against local and global process variations. Normalised energy metrics to 32 and 22 nm technologies shows that the proposed design achieves >57% energy savings in prior to the recent works.

Ternary Full Adder Using Multi-Threshold Voltage Graphene Barristors

Ternary logic circuit has been studied for several decades because it can provide simpler circuits and subsequently lower power consumption via succinct interconnects. We demonstrated a ternary full adder exhibiting a low power-delay-product of ~10−16 J, which is comparable to the binary equivalent circuit. The ternary full adder was modeled using device parameters extracted from the experimentally demonstrated multi-Vth ternary graphene barristors.

Plasma-assisted As implants for effective work function modulation of TiN/HfO2 gate stacks on germanium

The plasma assisted As doping (PLAD) technique is used to demonstrate multiple flatband voltages (multi-Vfb) on TiN/HfO2 Ge gate stacks for n-FinFET applications. Through detailed studies with varying doses, implant energies, and TiN cap thicknesses, we show that the PLAD As technique can be used to obtain effective work function (EWF) modulation from the near midgap to the conduction band edge (up to 280 meV) of Ge, a key technological requirement for multi-threshold voltage (VT) Ge n-FinFETs. Furthermore, there is no deterioration of key gate stack parameters such as gate leakage, effective oxide thickness, and gate/channel interface trap densities. From secondary ion mass spectroscopy data, we attribute the tuning of EWF to As accumulation and interfacial dipole formation at the TiN/HfO2 interface. The experimental observations are reinforced by ab initio simulations of near-interface As substitutions at the TiN/HfO2 interface. As substitution at N sites near the interface reduces the EWF, making it more suitable for n-MOS applications.

Multi-${V}_{\text{th}}$ Strategies of 7-nm node Nanosheet FETs With Limited Nanosheet Spacing

In this paper, multi-threshold voltage ( V th) scheme of 7-nm node nanosheet FETs (NSFETs) with narrow NS spacing were successfully achieved by metal-gate work function (WF) and channel doping ( $N _{\mathrm{ ch}}$ ) using fully calibrated 3-D TCAD simulations. The limited NS spacing, which allows TiN capping layer only, makes different WF between the edge and the middle part of NS circumference. Unfortunately, this causes non-linear V th shifts and dc performance degradation as a function of WF due to one-side turn-on phenomena between the edge and the middle part. Furthermore, the fixed WF of TiN capping layer limits V th shifts toward ultra-low-power applications. To enable multi- V th of NSFETs, several possible solutions are addressed: changing the $N _{\mathrm{ ch}}$ and the WF of TiN capping layer. The higher $N _{\mathrm{ ch}}$ enables lower off-state current while 50-nm-wide three-stacked NS decreases dc performance variations effectively. Changing the WF of TiN capping layer can extend V th margins, but degrade DC performance as a trade-off. Nonetheless, 7-nm node NSFETs adopting these techniques have multi- V th options to satisfy wide ranges from ultra-low-power to high-performance applications.