Multi-threshold Voltage Research Articles

Gate-length biasing for runtime-leakage control

Leakage power has become one of the most critical design concerns for the system level chip designer. While lowered supplies (and consequently, lowered threshold voltage) and aggressive clock gating can achieve dynamic power reduction, these techniques increase the leakage power and, therefore, causes its share of total power to increase. Manufacturers face the additional challenge of leakage variability: Recent data indicate that the leakage of microprocessor chips from a single 180-nm wafer can vary by as much as 20/spl times/. Previously proposed techniques for leakage-power reduction include the use of multiple supply and gate threshold voltages, and the assignment of input values to inactive gates, such that leakage is minimized. The additional design space afforded by the biasing of device gate lengths to reduce chip leakage power and its variability is studied. It is well known that leakage power decreases exponentially and delay increases linearly with increasing gate length. Thus, it is possible to increase gate length only marginally to take advantage of the exponential leakage reduction, while impairing performance only linearly. From a design-flow standpoint, the use of only slight increases in gate length preserves both pin and layout compatibility; therefore, the authors' technique can be applied as a postlayout enhancement step. The authors apply gate-length biasing only to those devices that do not appear in critical paths, thus assuring zero or negligible degradation in chip performance. To highlight the value of the technique, the multithreshold voltage technique, which is widely used for leakage reduction, is first applied and then gate-length biasing is used to show further reduction in leakage. Experimental results show that gate-length biasing reduces leakage by 24%-38% for the most commonly used cells, while incurring delay penalties of under 10%. Selective gate-length biasing at the circuit level reduces circuit leakage by up to 30% with no delay penalty. Leakage variability is reduced significantly by up to 41%, which may lead to substantial improvements in the manufacturing yield and the product cost. The use of gate-length biasing for leakage optimization of cell instances is also assessed, in which: 1) not all timing arcs are timing critical and/or 2) the rise and fall transitions are not both timing critical at the same time.

Multithreshold voltage low-swing/low-voltage techniques in logic gates

A low-power design circuit using low-swing voltage technique is proposed in this paper. The proposed technique could be used in order to decrease the power dissipation in three different types of logic gates namely the complementary pass-transistor logic (CPL), the cascade voltage switch logic (CVSL), and the domino logic. The main idea of the proposed technique is based on the replacement of the conventional CMOS inverter at the output of the logic gates with a new low-swing voltage inverter based on multithreshold voltage technology (LSIM). The inserted LSIM achieves a reduction in the static power dissipation, the dynamic power dissipation as the propagation delay time of the gates. To demonstrate the impact of the proposed technique in different applications, various types of circuits are designed for different conditions of: speed operation, load capacitance and supply voltages. In order to ensure the validity of the proposed technique in large circuit designs and fanout, a 8_bit Braun multiplier is designed in the three types of logic gates. SPICE simulation results for 3.3 V supply voltage using 0.5 μm multithreshold technology prove that 32%, 30% and 34%, reduction in power dissipation and 10%, 12% and 15% reduction in delay time could be achieved for the CPL, CVSL and domino logic gates respectively.

Low power high-speed multithreshold voltage CMOS bus architectures

Low power, high-speed bus architectures, based on low swing voltage technique, using multithreshold voltage transistors are proposed in this paper. Three different classes of driver/repeater/receiver circuits are introduced. The driver circuits are comprised of high threshold voltage MOSFET transistors, in order to reduce their output swing level voltage. For re-pulling up the low swing voltage to full swing, innovated high-speed, cross-coupled latch, voltage receiver circuits are used. In applications having high load capacitance due to long interconnections, novel repeater circuits based also on multithreshold voltage technology are introduced. Using 0.5 μm multithreshold voltage process technology and 1 V supply voltage, SPICE measurements showed up to 45% improvement in the power delay product.

Low power high-speed multithreshold voltage CMOS bus architectures

Low power, high-speed bus architectures, based on low swing voltage technique, using multithreshold voltage transistors are proposed in this paper. Three different classes of driver/repeater/receiver circuits are introduced. The driver circuits are comprised of high threshold voltage MOSFET transistors, in order to reduce their output swing level voltage. For re-pulling up the low swing voltage to full swing, innovated high-speed, cross-coupled latch, voltage receiver circuits are used. In applications having high load capacitance due to long interconnections, novel repeater circuits based also on multithreshold voltage technology are introduced. Using 0.5 μm multithreshold voltage process technology and 1 V supply voltage , SPICE measurements showed up to 45% improvement in the power delay product.

A 1-V, 10-MHz, 3.5-mW, 1-Mb MTCMOS SRAM: with charge-recycling input/output buffers

This paper presents a high-speed and low-power SRAM for portable equipment, which is operated by a single battery cell of around 1 V. Its memory cells are made up of high-threshold-voltage (high-V/sub th/) MOSFETs in order to suppress the power dissipation due to large subthreshold leakage currents. For designing peripheral circuitry, we use SRAM's special feature that input signals of each logic gate during the standby time can be predicted. Low-V/sub th/ MOSFETs are assigned for the critical paths of memory-cell access. The leakage current in each logic gate is reduced by high-V/sub th/ MOSFETs, which are cut off during standby. The high-V/sub th/, MOSFET in one logic gate can be shared with another logic gate in order to enlarge effective channel width. To shorten the readout time, a step-down boosted-wordline scheme suitable for current-sense readout and a new half-swing bidirectional double-rail bus are used. The data-writing time is halved by means of a pulse-reset wordline architecture. To reduce the power dissipation, a 32-divided memory array structure is employed with a new redundant address-decoding scheme. Also, data transition detectors and a charge-recycling technique are employed for reducing the power dissipation of data-I/O buffers. A 64-K-words/spl times/16-bits SRAM test chip, which was fabricated with a 0.5-/spl mu/m multithreshold voltage CMOS (MTCMOS) process, has demonstrated a 75-ns address access time at a 1-V power supply. The power dissipation during standby is 1.2 /spl mu/W, and that at a 10-MHz read operation with the modified checkerboard test pattern is 3.9 mW for 30-pF loads.