Multi-${V}_{\text{th}}$ Strategies of 7-nm node Nanosheet FETs With Limited Nanosheet Spacing

Abstract

In this paper, multi-threshold voltage ( V th) scheme of 7-nm node nanosheet FETs (NSFETs) with narrow NS spacing were successfully achieved by metal-gate work function (WF) and channel doping ( $N _{\mathrm{ ch}}$ ) using fully calibrated 3-D TCAD simulations. The limited NS spacing, which allows TiN capping layer only, makes different WF between the edge and the middle part of NS circumference. Unfortunately, this causes non-linear V th shifts and dc performance degradation as a function of WF due to one-side turn-on phenomena between the edge and the middle part. Furthermore, the fixed WF of TiN capping layer limits V th shifts toward ultra-low-power applications. To enable multi- V th of NSFETs, several possible solutions are addressed: changing the $N _{\mathrm{ ch}}$ and the WF of TiN capping layer. The higher $N _{\mathrm{ ch}}$ enables lower off-state current while 50-nm-wide three-stacked NS decreases dc performance variations effectively. Changing the WF of TiN capping layer can extend V th margins, but degrade DC performance as a trade-off. Nonetheless, 7-nm node NSFETs adopting these techniques have multi- V th options to satisfy wide ranges from ultra-low-power to high-performance applications.