A Novel Very Low-Complexity Multi-valued Logic Comparator in Nanoelectronics

Abstract

Using multi-valued logic (MVL) can reduce chip connections, which can have a direct effect on the chip area and connections power consumption. In the recent years, due to the high capability of nanotechnology in designing MVLs, some researchers have focused on this field. In designing MVL circuits, the low-complexity design is of great importance to fulfill the MVL aim. In this paper, a very low-complexity comparator for the MVL is proposed based on the multi-threshold voltage in CNTFETs. The proposed comparator in the 1-bit greater function only needs four transistors for all multi-valued logics; this results in a considerable transistor count reduction in comparison with the pervious works relying on 32 and 50 transistors in a ternary to quaternary case, respectively. Also, the number of 1-bit comparators is reduced from 50 and 74 transistors for the ternary to quaternary cases in the previous works to 12 in the proposed design. Additionally, the multi-digit comparator using the novel digit comparator is proposed. The simulation results using the Stanford 32 nm CNTFET library in HSPICE confirm the proper operation of the proposed comparator with the same range in PDP, in comparison with the previous works.